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Add the virtual timer irq to the list of interrupts we enable on secondary

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cores.
This commit is contained in:
Andrew Turner 2014-09-05 19:00:30 +00:00
parent 6cbf3f62e0
commit 5e5c172447
1 changed files with 4 additions and 1 deletions
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5
sys/arm/arm/gic.c
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@ -166,7 +166,10 @@ gic_init_secondary(void)
/* Enable interrupt distribution */
gic_d_write_4(GICD_CTLR, 0x01);
/* Activate IRQ 29-30, ie private timer (secure & non-secure) IRQs */
/*
* Activate the timer interrupts: virtual, secure, and non-secure.
*/
gic_d_write_4(GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
gic_d_write_4(GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
gic_d_write_4(GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
}