Add JMicron JMP202/JMP211 PHY driver.
This commit is contained in:
Pyun YongHyeon
parent
48972152ee
commit
6021a944af
379
sys/dev/mii/jmphy.c
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379
sys/dev/mii/jmphy.c
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@ -0,0 +1,379 @@
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/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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||||
* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for the JMicron JMP211 10/100/1000, JMP202 10/100 PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/jmphyreg.h>
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#include "miibus_if.h"
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static int jmphy_probe(device_t);
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static int jmphy_attach(device_t);
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static void jmphy_reset(struct mii_softc *);
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static uint16_t jmphy_anar(struct ifmedia_entry *);
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static int jmphy_auto(struct mii_softc *, struct ifmedia_entry *);
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struct jmphy_softc {
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struct mii_softc mii_sc;
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int mii_oui;
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int mii_model;
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int mii_rev;
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};
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static device_method_t jmphy_methods[] = {
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/* Device interface. */
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DEVMETHOD(device_probe, jmphy_probe),
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DEVMETHOD(device_attach, jmphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ NULL, NULL }
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};
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static devclass_t jmphy_devclass;
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static driver_t jmphy_driver = {
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"jmphy",
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jmphy_methods,
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sizeof(struct jmphy_softc)
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};
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DRIVER_MODULE(jmphy, miibus, jmphy_driver, jmphy_devclass, 0, 0);
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static int jmphy_service(struct mii_softc *, struct mii_data *, int);
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static void jmphy_status(struct mii_softc *);
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static const struct mii_phydesc jmphys[] = {
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MII_PHY_DESC(JMICRON, JMP202),
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MII_PHY_DESC(JMICRON, JMP211),
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MII_PHY_END
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};
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static int
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jmphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, jmphys, BUS_PROBE_DEFAULT));
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}
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static int
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jmphy_attach(device_t dev)
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{
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struct jmphy_softc *jsc;
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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jsc = device_get_softc(dev);
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sc = &jsc->mii_sc;
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = jmphy_service;
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sc->mii_pdata = mii;
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mii->mii_instance++;
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jsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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jsc->mii_model = MII_MODEL(ma->mii_id2);
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jsc->mii_rev = MII_REV(ma->mii_id2);
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if (bootverbose)
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device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n",
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jsc->mii_oui, jsc->mii_model, jsc->mii_rev);
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jmphy_reset(sc);
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t bmcr;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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bmcr = PHY_READ(sc, MII_BMCR);
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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if (jmphy_auto(sc, ife) != EJUSTRETURN)
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return (EINVAL);
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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return (0);
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0;
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break;
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}
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/* Check for link. */
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if ((PHY_READ(sc, JMPHY_SSR) & JMPHY_SSR_LINK_UP) != 0) {
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sc->mii_ticks = 0;
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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if (sc->mii_ticks <= sc->mii_anegticks)
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return (0);
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sc->mii_ticks = 0;
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jmphy_auto(sc, ife);
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break;
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}
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/* Update the media status. */
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jmphy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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jmphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmcr, ssr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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ssr = PHY_READ(sc, JMPHY_SSR);
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if ((ssr & JMPHY_SSR_LINK_UP) != 0)
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mii->mii_media_status |= IFM_ACTIVE;
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bmcr = PHY_READ(sc, MII_BMCR);
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if ((bmcr & BMCR_ISO) != 0) {
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if ((bmcr & BMCR_LOOP) != 0)
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mii->mii_media_active |= IFM_LOOP;
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if ((ssr & JMPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch ((ssr & JMPHY_SSR_SPEED_MASK)) {
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case JMPHY_SSR_SPEED_1000:
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mii->mii_media_active |= IFM_1000_T;
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/*
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* jmphy(4) got a valid link so reset mii_ticks.
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* Resetting mii_ticks is needed in order to
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* detect link loss after auto-negotiation.
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*/
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sc->mii_ticks = 0;
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break;
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case JMPHY_SSR_SPEED_100:
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mii->mii_media_active |= IFM_100_TX;
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sc->mii_ticks = 0;
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break;
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case JMPHY_SSR_SPEED_10:
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mii->mii_media_active |= IFM_10_T;
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sc->mii_ticks = 0;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if ((ssr & JMPHY_SSR_DUPLEX) != 0)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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/* XXX Flow-control. */
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#ifdef notyet
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
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if ((PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
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mii->mii_media_active |= IFM_ETH_MASTER;
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}
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#endif
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}
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static void
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jmphy_reset(struct mii_softc *sc)
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{
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struct jmphy_softc *jsc;
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int i;
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jsc = (struct jmphy_softc *)sc;
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/* Disable sleep mode. */
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PHY_WRITE(sc, JMPHY_TMCTL,
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PHY_READ(sc, JMPHY_TMCTL) & ~JMPHY_TMCTL_SLEEP_ENB);
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PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);
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for (i = 0; i < 1000; i++) {
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DELAY(1);
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if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
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break;
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}
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}
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static uint16_t
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jmphy_anar(struct ifmedia_entry *ife)
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{
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uint16_t anar;
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anar = 0;
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
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break;
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case IFM_1000_T:
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break;
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case IFM_100_TX:
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anar |= ANAR_TX | ANAR_TX_FD;
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break;
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case IFM_10_T:
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anar |= ANAR_10 | ANAR_10_FD;
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break;
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default:
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break;
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}
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return (anar);
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}
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static int
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jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife)
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{
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uint16_t anar, bmcr, gig;
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gig = 0;
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bmcr = PHY_READ(sc, MII_BMCR);
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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break;
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case IFM_1000_T:
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gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
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break;
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case IFM_100_TX:
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case IFM_10_T:
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break;
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case IFM_NONE:
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN);
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return (EJUSTRETURN);
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default:
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return (EINVAL);
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}
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if ((ife->ifm_media & IFM_LOOP) != 0)
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bmcr |= BMCR_LOOP;
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anar = jmphy_anar(ife);
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/* XXX Always advertise pause capability. */
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anar |= (3 << 10);
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if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
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#ifdef notyet
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struct mii_data *mii;
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mii = sc->mii_pdata;
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if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0)
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gig |= GTCR_MAN_MS | GTCR_MAN_ADV;
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#endif
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PHY_WRITE(sc, MII_100T2CR, gig);
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}
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PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
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PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
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return (EJUSTRETURN);
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}
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108
sys/dev/mii/jmphyreg.h
Normal file
108
sys/dev/mii/jmphyreg.h
Normal file
@ -0,0 +1,108 @@
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/*-
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* Copyright (c) 2008, Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_MII_JMPHYREG_H_
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#define _DEV_MII_JMPHYREG_H_
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/*
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* Registers for the JMicron JMC250 Gigabit PHY.
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*/
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/* PHY specific status register. */
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#define JMPHY_SSR 0x11
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#define JMPHY_SSR_SPEED_1000 0x8000
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#define JMPHY_SSR_SPEED_100 0x4000
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#define JMPHY_SSR_SPEED_10 0x0000
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#define JMPHY_SSR_SPEED_MASK 0xC000
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#define JMPHY_SSR_DUPLEX 0x2000
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#define JMPHY_SSR_SPD_DPLX_RESOLVED 0x0800
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#define JMPHY_SSR_LINK_UP 0x0400
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#define JMPHY_SSR_MDI_XOVER 0x0040
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#define JMPHY_SSR_INV_POLARITY 0x0002
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/* PHY specific cable length status register. */
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#define JMPHY_SCL 0x17
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#define JMPHY_SCL_CHAN_D_MASK 0xF000
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#define JMPHY_SCL_CHAN_C_MASK 0x0F00
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#define JMPHY_SCL_CHAN_B_MASK 0x00F0
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#define JMPHY_SCL_CHAN_A_MASK 0x000F
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#define JMPHY_SCL_LEN_35 0
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#define JMPHY_SCL_LEN_40 1
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#define JMPHY_SCL_LEN_50 2
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#define JMPHY_SCL_LEN_60 3
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#define JMPHY_SCL_LEN_70 4
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#define JMPHY_SCL_LEN_80 5
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#define JMPHY_SCL_LEN_90 6
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#define JMPHY_SCL_LEN_100 7
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#define JMPHY_SCL_LEN_110 8
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#define JMPHY_SCL_LEN_120 9
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#define JMPHY_SCL_LEN_130 10
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#define JMPHY_SCL_LEN_140 11
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#define JMPHY_SCL_LEN_150 12
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#define JMPHY_SCL_LEN_160 13
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#define JMPHY_SCL_LEN_170 14
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#define JMPHY_SCL_RSVD 15
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/* PHY specific LED control register 1. */
|
||||
#define JMPHY_LED_CTL1 0x18
|
||||
#define JMPHY_LED_BLINK_42MS 0x0000
|
||||
#define JMPHY_LED_BLINK_84MS 0x2000
|
||||
#define JMPHY_LED_BLINK_170MS 0x4000
|
||||
#define JMPHY_LED_BLINK_340MS 0x6000
|
||||
#define JMPHY_LED_BLINK_670MS 0x8000
|
||||
#define JMPHY_LED_BLINK_MASK 0xE000
|
||||
#define JMPHY_LED_FLP_GAP_MASK 0x1F00
|
||||
#define JMPHY_LED_FLP_GAP_DEFULT 0x1000
|
||||
#define JMPHY_LED2_POLARITY_MASK 0x0030
|
||||
#define JMPHY_LED1_POLARITY_MASK 0x000C
|
||||
#define JMPHY_LED0_POLARITY_MASK 0x0003
|
||||
#define JMPHY_LED_ON_LO_OFF_HI 0
|
||||
#define JMPHY_LED_ON_HI_OFF_HI 1
|
||||
#define JMPHY_LED_ON_LO_OFF_TS 2
|
||||
#define JMPHY_LED_ON_HI_OFF_TS 3
|
||||
|
||||
/* PHY specific LED control register 2. */
|
||||
#define JMPHY_LED_CTL2 0x19
|
||||
#define JMPHY_LED_NO_STRETCH 0x0000
|
||||
#define JMPHY_LED_STRETCH_42MS 0x2000
|
||||
#define JMPHY_LED_STRETCH_84MS 0x4000
|
||||
#define JMPHY_LED_STRETCH_170MS 0x6000
|
||||
#define JMPHY_LED_STRETCH_340MS 0x8000
|
||||
#define JMPHY_LED_STRETCH_670MS 0xB000
|
||||
#define JMPHY_LED_STRETCH_1300MS 0xC000
|
||||
#define JMPHY_LED_STRETCH_2700MS 0xE000
|
||||
#define JMPHY_LED2_MODE_MASK 0x0F00
|
||||
#define JMPHY_LED1_MODE_MASK 0x00F0
|
||||
#define JMPHY_LED0_MODE_MASK 0x000F
|
||||
|
||||
/* PHY specific test mode control register. */
|
||||
#define JMPHY_TMCTL 0x1A
|
||||
#define JMPHY_TMCTL_SLEEP_ENB 0x1000
|
||||
|
||||
#endif /* _DEV_MII_JMPHYREG_H_ */
|
||||
@ -60,6 +60,7 @@ oui ICPLUS 0x0090c3 IC Plus Corp.
|
||||
oui ICS 0x00a0be Integrated Circuit Systems
|
||||
oui INTEL 0x00aa00 Intel
|
||||
oui JATO 0x00e083 Jato Technologies
|
||||
oui JMICRON 0x001b8c JMicron Technologies
|
||||
oui LEVEL1 0x00207b Level 1
|
||||
oui NATSEMI 0x080017 National Semiconductor
|
||||
oui QUALSEMI 0x006051 Quality Semiconductor
|
||||
@ -178,6 +179,10 @@ model INTEL I82553C 0x0035 i82553 10/100 media interface
|
||||
/* Jato Technologies PHYs */
|
||||
model JATO BASEX 0x0000 Jato 1000baseX media interface
|
||||
|
||||
/* JMicron Technologies PHYs */
|
||||
model JMICRON JMP211 0x0021 JMP211 10/100/1000 media interface
|
||||
model JMICRON JMP202 0x0022 JMP202 10/100 media interface
|
||||
|
||||
/* Level 1 PHYs */
|
||||
model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user