Cleanup the interrupt code that deals with the busmaster bits.
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5e17543a23
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60279a3808
@ -139,18 +139,19 @@ ata_generic_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < 2; unit++) {
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for (unit = 0; unit < 2; unit++) {
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if (!(ch = ctlr->interrupt[unit].argument))
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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continue;
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (ch->dma) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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ATA_BMSTAT_INTERRUPT)
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continue;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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DELAY(1);
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}
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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@ -223,22 +224,24 @@ ata_acard_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < 2; unit++) {
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for (unit = 0; unit < 2; unit++) {
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if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
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if (ctlr->chip->cfg1 == ATPOLD && ctlr->locked_ch != unit)
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continue;
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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if (ch->dma) {
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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ATA_BMSTAT_INTERRUPT)
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continue;
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continue;
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ch = ctlr->interrupt[unit].argument;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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DELAY(1);
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DELAY(1);
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ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
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ATA_IDX_OUTB(ch, ATA_BMCMD_PORT,
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ATA_IDX_INB(ch, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
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ATA_IDX_INB(ch, ATA_BMCMD_PORT)&~ATA_BMCMD_START_STOP);
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DELAY(1);
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DELAY(1);
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}
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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@ -678,18 +681,21 @@ ata_highpoint_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < 2; unit++) {
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for (unit = 0; unit < 2; unit++) {
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if (!(ch = ctlr->interrupt[unit].argument))
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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continue;
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if (((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK)) &
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if (ch->dma) {
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(ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT))!=ATA_BMSTAT_INTERRUPT)
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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DELAY(1);
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ATA_BMSTAT_INTERRUPT)
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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}
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}
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}
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}
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@ -1210,7 +1216,6 @@ ata_promise_old_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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@ -1218,11 +1223,13 @@ ata_promise_old_intr(void *data)
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if (!(ch = ctlr->interrupt[unit].argument))
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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continue;
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if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
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if (ATA_INL(ctlr->r_io1, 0x1c) & (ch->unit ? 0x00004000 : 0x00000400)) {
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (ch->dma) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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ATA_BMSTAT_INTERRUPT)
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continue;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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DELAY(1);
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}
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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@ -1235,7 +1242,6 @@ ata_promise_tx2_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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@ -1244,11 +1250,13 @@ ata_promise_tx2_intr(void *data)
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continue;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
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ATA_IDX_OUTB(ch, ATA_BMDEVSPEC_0, 0x0b);
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if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
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if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_1) & 0x20) {
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (ch->dma) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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ATA_BMSTAT_INTERRUPT)
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continue;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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DELAY(1);
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}
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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@ -1668,7 +1676,6 @@ ata_sii_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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@ -1676,11 +1683,13 @@ ata_sii_intr(void *data)
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if (!(ch = ctlr->interrupt[unit].argument))
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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continue;
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if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
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if (ATA_IDX_INB(ch, ATA_BMDEVSPEC_0) & 0x08) {
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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if (ch->dma) {
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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ATA_BMSTAT_INTERRUPT)
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continue;
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continue;
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat|ATA_BMSTAT_INTERRUPT);
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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DELAY(1);
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}
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}
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ctlr->interrupt[unit].function(ch);
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ctlr->interrupt[unit].function(ch);
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@ -1693,26 +1702,28 @@ ata_cmd_intr(void *data)
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{
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{
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struct ata_pci_controller *ctlr = data;
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struct ata_pci_controller *ctlr = data;
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struct ata_channel *ch;
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struct ata_channel *ch;
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u_int8_t dmastat, reg71;
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u_int8_t reg71;
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int unit;
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int unit;
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/* implement this as a toggle instead to balance load XXX */
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/* implement this as a toggle instead to balance load XXX */
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for (unit = 0; unit < 2; unit++) {
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for (unit = 0; unit < 2; unit++) {
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if (!(ch = ctlr->interrupt[unit].argument))
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if (!(ch = ctlr->interrupt[unit].argument))
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continue;
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continue;
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if (!((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
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if (((reg71 = pci_read_config(device_get_parent(ch->dev), 0x71, 1)) &
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(ch->unit ? 0x08 : 0x04)))
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(ch->unit ? 0x08 : 0x04))) {
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continue;
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pci_write_config(device_get_parent(ch->dev), 0x71,
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pci_write_config(device_get_parent(ch->dev), 0x71,
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reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
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reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
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if (ch->dma) {
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if (ch->dma->flags & ATA_DMA_ACTIVE) {
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int bmstat = ATA_IDX_INB(ch, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
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if (!((dmastat = (ATA_IDX_INB(ch, ATA_BMSTAT_PORT) &
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ATA_BMSTAT_MASK)) & ATA_BMSTAT_INTERRUPT))
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if ((bmstat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
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continue;
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ATA_BMSTAT_INTERRUPT)
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
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continue;
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DELAY(1);
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, bmstat & ~ATA_BMSTAT_ERROR);
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DELAY(1);
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}
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ctlr->interrupt[unit].function(ch);
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}
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}
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ctlr->interrupt[unit].function(ch);
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}
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}
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}
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}
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