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Enable/Disable Ultra mode on a per target basis. This allows the driver

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to use the full range of settings from 3.6-20MHz on any target.
This commit is contained in:
Justin T. Gibbs 1996-05-21 18:32:23 +00:00
parent 18e75007df
commit 61538c3003
2 changed files with 21 additions and 3 deletions
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20
sys/dev/aic7xxx/aic7xxx.seq
View File

@ -39,7 +39,7 @@
*
*-M************************************************************************/
VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.33 1996/04/20 21:20:29 gibbs Exp $"
VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.34 1996/05/10 16:11:01 gibbs Exp $"
#include "../../dev/aic7xxx/aic7xxx_reg.h"
@ -253,13 +253,28 @@ select2:
call ndx_dtr
mov SCSIRATE,SINDIR
/*
* Initialize Ultra mode setting. ndx_dtr has left our target mask
* in A.
*/
and SINDEX,0xdf,SXFRCTL0 /* default to Ultra disabled */
test SCSIID, 0x80 jnz ultra_b /* Target ID > 7 */
test SBLKCTL, SELBUSB jnz ultra_b /* Second channel device */
test ULTRA_ENB,A jz set_sxfrctl0
or SINDEX, ULTRAEN jmp set_sxfrctl0
ultra_b:
test ULTRA_ENB_B,A jz set_sxfrctl0
or SINDEX, ULTRAEN
set_sxfrctl0:
mov SXFRCTL0,SINDEX
mvi SCSISEQ,ENAUTOATNP /*
* ATN on parity errors
* for "in" phases
*/
mvi CLRSINT1,CLRBUSFREE
mvi CLRSINT0,0x60 /* CLRSELDI|CLRSELDO */
/*
* Main loop for information transfer phases. If BSY is false, then
* we have a bus free condition, expected or not. Otherwise, wait
@ -283,6 +298,7 @@ ITloop:
cmp A,P_MESGIN je p_mesgin
mvi INTSTAT,BAD_PHASE /* unknown phase - signal driver */
jmp ITloop /* Try reading the bus again. */
p_dataout:
mvi DMAPARAMS,0x7d /*

4
sys/dev/aic7xxx/aic7xxx_reg.h
View File

@ -28,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: aic7xxx_reg.h,v 1.9 1996/05/10 16:11:03 gibbs Exp $
* $Id: aic7xxx_reg.h,v 1.10 1996/05/10 16:28:00 gibbs Exp $
*/
/*
@ -739,6 +739,8 @@
#define SAVED_LINKPTR 0x050
#define SAVED_SCBPTR 0x051
#define ULTRA_ENB 0x052
#define ULTRA_ENB_B 0x053
#define SCSICONF 0x05a
#define RESET_SCSI 0x40