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Add support for Intel's i820/i840/i845/i850/i860 chipset.

Browse Source 
Submitted by:	nork@cityfujisawa.ne.jp (Norikatsu Shigemura)
PR:		kern/31559, kern/31825
MFC after:	1 week
This commit is contained in:
Jun Kuriyama 2001-11-08 16:03:23 +00:00
parent eacb362f8a
commit 6183dc49fb
4 changed files with 212 additions and 22 deletions
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109
sys/dev/agp/agp_intel.c
View File

@ -79,6 +79,21 @@ agp_intel_match(device_t dev)
case 0x11308086: case 0x11308086:
return ("Intel 82815 (i815 GMCH) host to PCI bridge"); return ("Intel 82815 (i815 GMCH) host to PCI bridge");
case 0x25008086:
return ("Intel 82820 host to AGP bridge");
case 0x1a218086:
return ("Intel 82840 host to AGP bridge");
case 0x1a308086:
return ("Intel 82845 host to AGP bridge");
case 0x25308086:
return ("Intel 82850 host to AGP bridge");
case 0x25318086:
return ("Intel 82860 host to AGP bridge");
}; };
if (pci_get_vendor(dev) == 0x8086) if (pci_get_vendor(dev) == 0x8086)
@ -107,6 +122,7 @@ agp_intel_attach(device_t dev)
{ {
struct agp_intel_softc *sc = device_get_softc(dev); struct agp_intel_softc *sc = device_get_softc(dev);
struct agp_gatt *gatt; struct agp_gatt *gatt;
u_int32_t type = pci_get_devid(dev);
int error; int error;
error = agp_generic_attach(dev); error = agp_generic_attach(dev);
@ -135,11 +151,52 @@ agp_intel_attach(device_t dev)
pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
/* Enable things, clear errors etc. */ /* Enable things, clear errors etc. */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); switch (type) {
pci_write_config(dev, AGP_INTEL_NBXCFG, case 0x1a218086: /* i840 */
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) case 0x25308086: /* i850 */
& ~(1 << 10)) | (1 << 9), 4); case 0x25318086: /* i860 */
pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
| (1 << 9)), 2);
break;
case 0x25008086: /* i820 */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_I820_RDCR,
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
| (1 << 1)), 1);
break;
case 0x1a308086: /* i845 */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
| (1 << 1)), 1);
break;
default: /* Intel Generic (maybe) */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
pci_write_config(dev, AGP_INTEL_NBXCFG,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 10)) | (1 << 9), 4);
}
switch (type) {
case 0x1a218086: /* i840 */
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
break;
case 0x25008086: /* i820 */
case 0x1a308086: /* i845 */
case 0x25308086: /* i850 */
case 0x25318086: /* i860 */
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
break;
default: /* Intel Generic (maybe) */
pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
}
return 0; return 0;
} }
@ -148,18 +205,48 @@ static int
agp_intel_detach(device_t dev) agp_intel_detach(device_t dev)
{ {
struct agp_intel_softc *sc = device_get_softc(dev); struct agp_intel_softc *sc = device_get_softc(dev);
u_int32_t type = pci_get_devid(dev);
int error; int error;
error = agp_generic_detach(dev); error = agp_generic_detach(dev);
if (error) if (error)
return error; return error;
printf("%s: set NBXCFG to %x\n", __FUNCTION__, switch (type) {
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) case 0x1a218086: /* i840 */
& ~(1 << 9))); case 0x25308086: /* i850 */
pci_write_config(dev, AGP_INTEL_NBXCFG, case 0x25318086: /* i860 */
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
& ~(1 << 9)), 4); (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
& ~(1 << 9)));
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
& ~(1 << 9)), 2);
case 0x25008086: /* i820 */
printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
& ~(1 << 1)));
pci_write_config(dev, AGP_INTEL_I820_RDCR,
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
& ~(1 << 1)), 1);
case 0x1a308086: /* i845 */
printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
& ~(1 << 1)));
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
& ~(1 << 1)), 1);
default: /* Intel Generic (maybe) */
printf("%s: set NBXCFG to %x\n", __FUNCTION__,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 9)));
pci_write_config(dev, AGP_INTEL_NBXCFG,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 9)), 4);
}
pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
AGP_SET_APERTURE(dev, sc->initial_aperture); AGP_SET_APERTURE(dev, sc->initial_aperture);
agp_free_gatt(sc->gatt); agp_free_gatt(sc->gatt);

8
sys/dev/agp/agpreg.h
View File

@ -56,6 +56,14 @@
#define AGP_INTEL_APSIZE 0xb4 #define AGP_INTEL_APSIZE 0xb4
#define AGP_INTEL_ATTBASE 0xb8 #define AGP_INTEL_ATTBASE 0xb8
/*
* Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets.
*/
#define AGP_INTEL_MCHCFG 0x50
#define AGP_INTEL_I820_RDCR 0x51
#define AGP_INTEL_I845_MCHCFG 0x51
#define AGP_INTEL_I8XX_ERRSTS 0xc8
/* /*
* Config offsets for VIA AGP chipsets. * Config offsets for VIA AGP chipsets.
*/ */

109
sys/pci/agp_intel.c
View File

@ -79,6 +79,21 @@ agp_intel_match(device_t dev)
case 0x11308086: case 0x11308086:
return ("Intel 82815 (i815 GMCH) host to PCI bridge"); return ("Intel 82815 (i815 GMCH) host to PCI bridge");
case 0x25008086:
return ("Intel 82820 host to AGP bridge");
case 0x1a218086:
return ("Intel 82840 host to AGP bridge");
case 0x1a308086:
return ("Intel 82845 host to AGP bridge");
case 0x25308086:
return ("Intel 82850 host to AGP bridge");
case 0x25318086:
return ("Intel 82860 host to AGP bridge");
}; };
if (pci_get_vendor(dev) == 0x8086) if (pci_get_vendor(dev) == 0x8086)
@ -107,6 +122,7 @@ agp_intel_attach(device_t dev)
{ {
struct agp_intel_softc *sc = device_get_softc(dev); struct agp_intel_softc *sc = device_get_softc(dev);
struct agp_gatt *gatt; struct agp_gatt *gatt;
u_int32_t type = pci_get_devid(dev);
int error; int error;
error = agp_generic_attach(dev); error = agp_generic_attach(dev);
@ -135,11 +151,52 @@ agp_intel_attach(device_t dev)
pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
/* Enable things, clear errors etc. */ /* Enable things, clear errors etc. */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); switch (type) {
pci_write_config(dev, AGP_INTEL_NBXCFG, case 0x1a218086: /* i840 */
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) case 0x25308086: /* i850 */
& ~(1 << 10)) | (1 << 9), 4); case 0x25318086: /* i860 */
pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
| (1 << 9)), 2);
break;
case 0x25008086: /* i820 */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_I820_RDCR,
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
| (1 << 1)), 1);
break;
case 0x1a308086: /* i845 */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4);
pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
| (1 << 1)), 1);
break;
default: /* Intel Generic (maybe) */
pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
pci_write_config(dev, AGP_INTEL_NBXCFG,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 10)) | (1 << 9), 4);
}
switch (type) {
case 0x1a218086: /* i840 */
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
break;
case 0x25008086: /* i820 */
case 0x1a308086: /* i845 */
case 0x25308086: /* i850 */
case 0x25318086: /* i860 */
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2);
break;
default: /* Intel Generic (maybe) */
pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
}
return 0; return 0;
} }
@ -148,18 +205,48 @@ static int
agp_intel_detach(device_t dev) agp_intel_detach(device_t dev)
{ {
struct agp_intel_softc *sc = device_get_softc(dev); struct agp_intel_softc *sc = device_get_softc(dev);
u_int32_t type = pci_get_devid(dev);
int error; int error;
error = agp_generic_detach(dev); error = agp_generic_detach(dev);
if (error) if (error)
return error; return error;
printf("%s: set NBXCFG to %x\n", __FUNCTION__, switch (type) {
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) case 0x1a218086: /* i840 */
& ~(1 << 9))); case 0x25308086: /* i850 */
pci_write_config(dev, AGP_INTEL_NBXCFG, case 0x25318086: /* i860 */
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4) printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
& ~(1 << 9)), 4); (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
& ~(1 << 9)));
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
& ~(1 << 9)), 2);
case 0x25008086: /* i820 */
printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
& ~(1 << 1)));
pci_write_config(dev, AGP_INTEL_I820_RDCR,
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
& ~(1 << 1)), 1);
case 0x1a308086: /* i845 */
printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
& ~(1 << 1)));
pci_write_config(dev, AGP_INTEL_MCHCFG,
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
& ~(1 << 1)), 1);
default: /* Intel Generic (maybe) */
printf("%s: set NBXCFG to %x\n", __FUNCTION__,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 9)));
pci_write_config(dev, AGP_INTEL_NBXCFG,
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
& ~(1 << 9)), 4);
}
pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
AGP_SET_APERTURE(dev, sc->initial_aperture); AGP_SET_APERTURE(dev, sc->initial_aperture);
agp_free_gatt(sc->gatt); agp_free_gatt(sc->gatt);

8
sys/pci/agpreg.h
View File

@ -56,6 +56,14 @@
#define AGP_INTEL_APSIZE 0xb4 #define AGP_INTEL_APSIZE 0xb4
#define AGP_INTEL_ATTBASE 0xb8 #define AGP_INTEL_ATTBASE 0xb8
/*
* Config offsets for Intel i820/i840/i845/i850/i860 AGP chipsets.
*/
#define AGP_INTEL_MCHCFG 0x50
#define AGP_INTEL_I820_RDCR 0x51
#define AGP_INTEL_I845_MCHCFG 0x51
#define AGP_INTEL_I8XX_ERRSTS 0xc8
/* /*
* Config offsets for VIA AGP chipsets. * Config offsets for VIA AGP chipsets.
*/ */