Much better fix/support for the 83c795 based cards (the new SMC EtherEZ)
by steve@simon.chi.il.us (Steven E. Piette). Minor changes by me.
This commit is contained in:
David Greenman
parent
e79b19bc05
commit
61be67ba43
@ -13,7 +13,7 @@
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* the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
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* and a variety of similar clones.
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*
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* $Id: if_ed.c,v 1.63 1995/01/04 21:10:17 davidg Exp $
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* $Id: if_ed.c,v 1.64 1995/01/15 00:18:17 wollman Exp $
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*/
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#include "ed.h"
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@ -401,18 +401,32 @@ ed_probe_WD80x3(isa_dev)
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sc->is790 = 1;
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break;
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case ED_TYPE_SMC8216T:
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(unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0;
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if ((unsigned int) *(isa_dev->id_maddr+8192)) {
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sc->type_str = "SMC8216T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8216T";
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
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case ED_WD790_RAR_SZ64:
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memsize = 65536;
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break;
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case ED_WD790_RAR_SZ32:
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memsize = 32768;
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break;
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case ED_WD790_RAR_SZ16:
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memsize = 16384;
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break;
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case ED_WD790_RAR_SZ8:
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sc->type_str = "SMC8416T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8416T";
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memsize = 8192;
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} else {
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sc->type_str = "SMC8216T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8216T";
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memsize = 16384;
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break;
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}
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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isa16bit = 1;
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sc->is790 = 1;
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break;
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@ -447,6 +461,30 @@ ed_probe_WD80x3(isa_dev)
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isa16bit = 0;
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memsize = 8192;
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}
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
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case ED_WD790_RAR_SZ64:
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memsize = 65536;
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break;
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case ED_WD790_RAR_SZ32:
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memsize = 32768;
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break;
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case ED_WD790_RAR_SZ16:
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memsize = 16384;
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break;
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case ED_WD790_RAR_SZ8:
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memsize = 8192;
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break;
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}
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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}
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#if ED_DEBUG
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printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
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sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
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@ -585,11 +623,11 @@ ed_probe_WD80x3(isa_dev)
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sc->cr_proto = ED_CR_RD2;
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} else {
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
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outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
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outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
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outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
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((kvtop(sc->mem_start) >> 11) & 0x40) |
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(inb(sc->asic_addr + 0x0b) & 0xb0));
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outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
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(inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
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outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
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sc->cr_proto = 0;
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}
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@ -6,7 +6,7 @@
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* of this software, nor does the author assume any responsibility
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* for damages incurred with its use.
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*
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* $Id: if_edreg.h,v 1.15 1994/08/02 07:39:30 davidg Exp $
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* $Id: if_edreg.h,v 1.16 1994/08/04 17:42:35 davidg Exp $
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*/
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/*
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* National Semiconductor DS8390 NIC register definitions
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@ -704,6 +704,25 @@ struct ed_ring {
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#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
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/*
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* REV/IOPA Revision / I/O Pipe register for the 83C79X
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*/
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#define ED_WD790_REV 7
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#define ED_WD790 0x20
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#define ED_WD795 0x40
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/*
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* 79X RAM Address Register (RAR)
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* Enabled with SWH bit=1 in HWR register
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*/
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#define ED_WD790_RAR 0x0b
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#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
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#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
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#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
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#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
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/*
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* General Control Register (GCR)
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* Enabled with SWH bit=1 in HWR register
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@ -714,6 +733,7 @@ struct ed_ring {
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#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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@ -13,7 +13,7 @@
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* the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
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* and a variety of similar clones.
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*
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* $Id: if_ed.c,v 1.63 1995/01/04 21:10:17 davidg Exp $
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* $Id: if_ed.c,v 1.64 1995/01/15 00:18:17 wollman Exp $
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*/
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#include "ed.h"
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@ -401,18 +401,32 @@ ed_probe_WD80x3(isa_dev)
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sc->is790 = 1;
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break;
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case ED_TYPE_SMC8216T:
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(unsigned int) *(isa_dev->id_maddr+8192) = (unsigned int)0;
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if ((unsigned int) *(isa_dev->id_maddr+8192)) {
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sc->type_str = "SMC8216T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8216T";
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
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case ED_WD790_RAR_SZ64:
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memsize = 65536;
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break;
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case ED_WD790_RAR_SZ32:
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memsize = 32768;
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break;
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case ED_WD790_RAR_SZ16:
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memsize = 16384;
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break;
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case ED_WD790_RAR_SZ8:
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sc->type_str = "SMC8416T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8416T";
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memsize = 8192;
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} else {
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sc->type_str = "SMC8216T";
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sc->kdc.kdc_description =
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"Ethernet adapter: SMC 8216T";
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memsize = 16384;
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break;
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}
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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isa16bit = 1;
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sc->is790 = 1;
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break;
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@ -447,6 +461,30 @@ ed_probe_WD80x3(isa_dev)
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isa16bit = 0;
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memsize = 8192;
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}
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
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switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
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case ED_WD790_RAR_SZ64:
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memsize = 65536;
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break;
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case ED_WD790_RAR_SZ32:
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memsize = 32768;
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break;
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case ED_WD790_RAR_SZ16:
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memsize = 16384;
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break;
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case ED_WD790_RAR_SZ8:
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memsize = 8192;
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break;
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}
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outb(sc->asic_addr + ED_WD790_HWR,
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inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
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}
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#if ED_DEBUG
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printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
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sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
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@ -585,11 +623,11 @@ ed_probe_WD80x3(isa_dev)
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sc->cr_proto = ED_CR_RD2;
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} else {
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) | 0x80));
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outb(sc->asic_addr + 0x0b, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
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outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
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outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
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((kvtop(sc->mem_start) >> 11) & 0x40) |
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(inb(sc->asic_addr + 0x0b) & 0xb0));
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outb(sc->asic_addr + 0x04, (inb(sc->asic_addr + 0x04) & ~0x80));
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(inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
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outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
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sc->cr_proto = 0;
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}
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@ -6,7 +6,7 @@
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* of this software, nor does the author assume any responsibility
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* for damages incurred with its use.
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*
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* $Id: if_edreg.h,v 1.15 1994/08/02 07:39:30 davidg Exp $
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* $Id: if_edreg.h,v 1.16 1994/08/04 17:42:35 davidg Exp $
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*/
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/*
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* National Semiconductor DS8390 NIC register definitions
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@ -704,6 +704,25 @@ struct ed_ring {
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#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
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/*
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* REV/IOPA Revision / I/O Pipe register for the 83C79X
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*/
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#define ED_WD790_REV 7
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#define ED_WD790 0x20
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#define ED_WD795 0x40
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/*
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* 79X RAM Address Register (RAR)
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* Enabled with SWH bit=1 in HWR register
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*/
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#define ED_WD790_RAR 0x0b
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#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
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#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
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#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
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#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
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/*
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* General Control Register (GCR)
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* Enabled with SWH bit=1 in HWR register
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@ -714,6 +733,7 @@ struct ed_ring {
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#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
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#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
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#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
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#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
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/*
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* The three bits of the encoded IRQ are decoded as follows:
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*
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