Upgrade ENA HAL to the latest version (26/10/20)
Add support for the ENI metrics, bug fix for destroying wait event and also other minor bug fixes, improvements, etc. Submitted by: Ido Segev <idose@amazon.com> Obtained from: Amazon, Inc.
This commit is contained in:
Marcin Wojtas
parent
d5fc5012bb
commit
62023a0e6d
35
ena_com.h
35
ena_com.h
@ -1,5 +1,5 @@
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/*-
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* BSD LICENSE
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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@ -328,6 +328,7 @@ struct ena_com_dev {
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void __iomem *mem_bar;
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void *dmadev;
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void *bus;
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ena_netdev *net_device;
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enum ena_admin_placement_policy_type tx_mem_queue_type;
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u32 tx_max_header_size;
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@ -365,7 +366,6 @@ struct ena_com_dev_get_features_ctx {
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struct ena_admin_feature_offload_desc offload;
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struct ena_admin_ena_hw_hints hw_hints;
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struct ena_admin_feature_llq_desc llq;
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struct ena_admin_feature_rss_ind_table ind_table;
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};
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struct ena_com_create_io_ctx {
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@ -550,7 +550,7 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
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* This method goes over the async event notification queue and calls the proper
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* aenq handler.
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*/
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void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
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void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data);
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/* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
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* @ena_dev: ENA communication layer struct
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@ -630,6 +630,15 @@ int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
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int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
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struct ena_admin_basic_stats *stats);
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/* ena_com_get_eni_stats - Get extended network interface statistics
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* @ena_dev: ENA communication layer struct
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* @stats: stats return value
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*
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* @return: 0 on Success and negative value otherwise.
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*/
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int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
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struct ena_admin_eni_stats *stats);
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/* ena_com_set_dev_mtu - Configure the device mtu.
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* @ena_dev: ENA communication layer struct
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* @mtu: mtu value
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@ -963,6 +972,26 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
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struct ena_admin_feature_llq_desc *llq_features,
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struct ena_llq_configurations *llq_default_config);
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/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq.
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* @io_sq: IO submit queue struct
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*
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* @return - ena_com_dev struct extracted from io_sq
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*/
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static inline struct ena_com_dev *ena_com_io_sq_to_ena_dev(struct ena_com_io_sq *io_sq)
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{
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return container_of(io_sq, struct ena_com_dev, io_sq_queues[io_sq->qid]);
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}
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/* ena_com_io_cq_to_ena_dev - Extract ena_com_dev using contained field io_cq.
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* @io_sq: IO submit queue struct
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*
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* @return - ena_com_dev struct extracted from io_sq
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*/
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static inline struct ena_com_dev *ena_com_io_cq_to_ena_dev(struct ena_com_io_cq *io_cq)
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{
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return container_of(io_cq, struct ena_com_dev, io_cq_queues[io_cq->qid]);
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}
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static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
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{
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return ena_dev->adaptive_coalescing;
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@ -1,5 +1,5 @@
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/*-
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* BSD LICENSE
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
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* All rights reserved.
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@ -36,6 +36,8 @@
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#define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
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#define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
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#define ENA_ADMIN_RSS_KEY_PARTS 10
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enum ena_admin_aq_opcode {
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ENA_ADMIN_CREATE_SQ = 1,
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ENA_ADMIN_DESTROY_SQ = 2,
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@ -58,6 +60,7 @@ enum ena_admin_aq_completion_status {
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ENA_ADMIN_RESOURCE_BUSY = 7,
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};
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/* subcommands for the set/get feature admin commands */
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enum ena_admin_aq_feature_id {
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ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
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ENA_ADMIN_MAX_QUEUES_NUM = 2,
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@ -68,7 +71,7 @@ enum ena_admin_aq_feature_id {
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ENA_ADMIN_MAX_QUEUES_EXT = 7,
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ENA_ADMIN_RSS_HASH_FUNCTION = 10,
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ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
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ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12,
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ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
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ENA_ADMIN_MTU = 14,
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ENA_ADMIN_RSS_HASH_INPUT = 18,
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ENA_ADMIN_INTERRUPT_MODERATION = 20,
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@ -122,6 +125,8 @@ enum ena_admin_completion_policy_type {
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enum ena_admin_get_stats_type {
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ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
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ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
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/* extra HW stats for specific network interface */
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ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
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};
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enum ena_admin_get_stats_scope {
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@ -198,7 +203,7 @@ struct ena_admin_acq_common_desc {
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uint16_t extended_status;
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/* indicates to the driver which AQ entry has been consumed by the
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* device and could be reused
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* device and could be reused
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*/
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uint16_t sq_head_indx;
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};
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@ -243,8 +248,8 @@ struct ena_admin_aq_create_sq_cmd {
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*/
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uint8_t sq_caps_3;
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/* associated completion queue id. This CQ must be created prior to
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* SQ creation
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/* associated completion queue id. This CQ must be created prior to SQ
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* creation
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*/
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uint16_t cq_idx;
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@ -383,7 +388,7 @@ struct ena_admin_aq_get_stats_cmd {
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uint16_t queue_idx;
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/* device id, value 0xFFFF means mine. only privileged device can get
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* stats of other device
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* stats of other device
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*/
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uint16_t device_id;
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};
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@ -415,10 +420,43 @@ struct ena_admin_basic_stats {
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uint32_t tx_drops_high;
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};
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/* ENI Statistics Command. */
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struct ena_admin_eni_stats {
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/* The number of packets shaped due to inbound aggregate BW
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* allowance being exceeded
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*/
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uint64_t bw_in_allowance_exceeded;
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/* The number of packets shaped due to outbound aggregate BW
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* allowance being exceeded
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*/
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uint64_t bw_out_allowance_exceeded;
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/* The number of packets shaped due to PPS allowance being exceeded */
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uint64_t pps_allowance_exceeded;
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/* The number of packets shaped due to connection tracking
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* allowance being exceeded and leading to failure in establishment
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* of new connections
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*/
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uint64_t conntrack_allowance_exceeded;
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/* The number of packets shaped due to linklocal packet rate
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* allowance being exceeded
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*/
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uint64_t linklocal_allowance_exceeded;
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};
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struct ena_admin_acq_get_stats_resp {
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struct ena_admin_acq_common_desc acq_common_desc;
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struct ena_admin_basic_stats basic_stats;
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union {
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uint64_t raw[7];
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struct ena_admin_basic_stats basic_stats;
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struct ena_admin_eni_stats eni_stats;
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} u;
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};
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struct ena_admin_get_set_feature_common_desc {
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@ -432,8 +470,8 @@ struct ena_admin_get_set_feature_common_desc {
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uint8_t feature_id;
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/* The driver specifies the max feature version it supports and the
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* device responds with the currently supported feature version. The
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* field is zero based
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* device responds with the currently supported feature version. The
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* field is zero based
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*/
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uint8_t feature_version;
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@ -445,7 +483,9 @@ struct ena_admin_device_attr_feature_desc {
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uint32_t device_version;
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/* bitmap of ena_admin_aq_feature_id */
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/* bitmap of ena_admin_aq_feature_id, which represents supported
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* subcommands for the set/get feature admin commands.
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*/
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uint32_t supported_features;
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uint32_t reserved3;
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@ -531,32 +571,30 @@ struct ena_admin_feature_llq_desc {
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uint32_t max_llq_depth;
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/* specify the header locations the device supports. bitfield of
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* enum ena_admin_llq_header_location.
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/* specify the header locations the device supports. bitfield of enum
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* ena_admin_llq_header_location.
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*/
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uint16_t header_location_ctrl_supported;
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/* the header location the driver selected to use. */
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uint16_t header_location_ctrl_enabled;
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/* if inline header is specified - this is the size of descriptor
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* list entry. If header in a separate ring is specified - this is
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* the size of header ring entry. bitfield of enum
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* ena_admin_llq_ring_entry_size. specify the entry sizes the device
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* supports
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/* if inline header is specified - this is the size of descriptor list
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* entry. If header in a separate ring is specified - this is the size
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* of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
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* specify the entry sizes the device supports
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*/
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uint16_t entry_size_ctrl_supported;
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/* the entry size the driver selected to use. */
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uint16_t entry_size_ctrl_enabled;
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/* valid only if inline header is specified. First entry associated
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* with the packet includes descriptors and header. Rest of the
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* entries occupied by descriptors. This parameter defines the max
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* number of descriptors precedding the header in the first entry.
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* The field is bitfield of enum
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* ena_admin_llq_num_descs_before_header and specify the values the
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* device supports
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/* valid only if inline header is specified. First entry associated with
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* the packet includes descriptors and header. Rest of the entries
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* occupied by descriptors. This parameter defines the max number of
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* descriptors precedding the header in the first entry. The field is
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* bitfield of enum ena_admin_llq_num_descs_before_header and specify
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* the values the device supports
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*/
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uint16_t desc_num_before_header_supported;
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@ -564,7 +602,7 @@ struct ena_admin_feature_llq_desc {
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uint16_t desc_num_before_header_enabled;
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/* valid only if inline was chosen. bitfield of enum
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* ena_admin_llq_stride_ctrl
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* ena_admin_llq_stride_ctrl
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*/
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uint16_t descriptors_stride_ctrl_supported;
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@ -574,8 +612,8 @@ struct ena_admin_feature_llq_desc {
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/* reserved */
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uint32_t reserved1;
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/* accelerated low latency queues requirment. driver needs to
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* support those requirments in order to use accelerated llq
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/* accelerated low latency queues requirement. driver needs to
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* support those requirements in order to use accelerated llq
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*/
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struct ena_admin_accel_mode_req accel_mode;
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};
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@ -599,8 +637,8 @@ struct ena_admin_queue_ext_feature_fields {
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uint32_t max_tx_header_size;
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/* Maximum Descriptors number, including meta descriptor, allowed for
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* a single Tx packet
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/* Maximum Descriptors number, including meta descriptor, allowed for a
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* single Tx packet
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*/
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uint16_t max_per_packet_tx_descs;
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@ -623,8 +661,8 @@ struct ena_admin_queue_feature_desc {
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uint32_t max_header_size;
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/* Maximum Descriptors number, including meta descriptor, allowed for
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* a single Tx packet
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/* Maximum Descriptors number, including meta descriptor, allowed for a
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* single Tx packet
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*/
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uint16_t max_packet_tx_descs;
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@ -720,11 +758,11 @@ enum ena_admin_hash_functions {
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};
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struct ena_admin_feature_rss_flow_hash_control {
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uint32_t keys_num;
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uint32_t key_parts;
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uint32_t reserved;
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uint32_t key[10];
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uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
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};
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struct ena_admin_feature_rss_flow_hash_function {
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@ -859,11 +897,12 @@ struct ena_admin_host_info {
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uint16_t reserved;
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/* 0 : mutable_rss_table_size
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/* 0 : reserved
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* 1 : rx_offset
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* 2 : interrupt_moderation
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* 3 : map_rx_buf_bidirectional
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* 31:4 : reserved
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* 3 : rx_buf_mirroring
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* 4 : rss_configurable_function_key
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* 31:5 : reserved
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*/
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uint32_t driver_supported_features;
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};
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@ -945,7 +984,7 @@ struct ena_admin_queue_ext_feature_desc {
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struct ena_admin_queue_ext_feature_fields max_queue_ext;
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uint32_t raw[10];
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} ;
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};
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};
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struct ena_admin_get_feat_resp {
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@ -1028,7 +1067,7 @@ struct ena_admin_set_feat_resp {
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struct ena_admin_aenq_common_desc {
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uint16_t group;
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uint16_t syndrom;
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uint16_t syndrome;
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/* 0 : phase
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* 7:1 : reserved - MBZ
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@ -1052,7 +1091,7 @@ enum ena_admin_aenq_group {
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ENA_ADMIN_AENQ_GROUPS_NUM = 5,
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};
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enum ena_admin_aenq_notification_syndrom {
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enum ena_admin_aenq_notification_syndrome {
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ENA_ADMIN_SUSPEND = 0,
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ENA_ADMIN_RESUME = 1,
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ENA_ADMIN_UPDATE_HINTS = 2,
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@ -1181,13 +1220,14 @@ struct ena_admin_ena_mmio_req_read_less_resp {
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#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
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#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
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#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
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#define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0)
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
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#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
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#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
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#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3
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#define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3)
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#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
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#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
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#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
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#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
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/* feature_rss_ind_table */
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#define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
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@ -1609,16 +1649,6 @@ static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, ui
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p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
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}
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static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p)
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{
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return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
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}
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static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val)
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{
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p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK;
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}
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static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
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{
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return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
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@ -1639,14 +1669,24 @@ static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin
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p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
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}
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static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p)
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static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p)
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{
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return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT;
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return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT;
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}
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static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val)
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static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val)
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{
|
||||
p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK;
|
||||
p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
|
||||
{
|
||||
return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
|
||||
}
|
||||
|
||||
static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
|
||||
{
|
||||
p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
|
||||
}
|
||||
|
||||
static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
@ -30,5 +30,5 @@
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#define ENA_GEN_DATE "Mon Apr 20 15:41:59 DST 2020"
|
||||
#define ENA_GEN_COMMIT "daa45ac"
|
||||
#define ENA_GEN_DATE "Fri Sep 18 17:09:00 IDT 2020"
|
||||
#define ENA_GEN_COMMIT "0f80d82"
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
|
||||
129
ena_eth_com.c
129
ena_eth_com.c
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
@ -85,12 +85,14 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,
|
||||
|
||||
if (is_llq_max_tx_burst_exists(io_sq)) {
|
||||
if (unlikely(!io_sq->entries_in_tx_burst_left)) {
|
||||
ena_trc_err("Error: trying to send more packets than tx burst allows\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Error: trying to send more packets than tx burst allows\n");
|
||||
return ENA_COM_NO_SPACE;
|
||||
}
|
||||
|
||||
io_sq->entries_in_tx_burst_left--;
|
||||
ena_trc_dbg("decreasing entries_in_tx_burst_left of queue %d to %d\n",
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Decreasing entries_in_tx_burst_left of queue %d to %d\n",
|
||||
io_sq->qid, io_sq->entries_in_tx_burst_left);
|
||||
}
|
||||
|
||||
@ -129,12 +131,14 @@ static int ena_com_write_header_to_bounce(struct ena_com_io_sq *io_sq,
|
||||
llq_info->descs_num_before_header * io_sq->desc_entry_size;
|
||||
|
||||
if (unlikely((header_offset + header_len) > llq_info->desc_list_entry_size)) {
|
||||
ena_trc_err("trying to write header larger than llq entry can accommodate\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Trying to write header larger than llq entry can accommodate\n");
|
||||
return ENA_COM_FAULT;
|
||||
}
|
||||
|
||||
if (unlikely(!bounce_buffer)) {
|
||||
ena_trc_err("bounce buffer is NULL\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Bounce buffer is NULL\n");
|
||||
return ENA_COM_FAULT;
|
||||
}
|
||||
|
||||
@ -152,7 +156,8 @@ static void *get_sq_desc_llq(struct ena_com_io_sq *io_sq)
|
||||
bounce_buffer = pkt_ctrl->curr_bounce_buf;
|
||||
|
||||
if (unlikely(!bounce_buffer)) {
|
||||
ena_trc_err("bounce buffer is NULL\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Bounce buffer is NULL\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@ -177,7 +182,8 @@ static int ena_com_close_bounce_buffer(struct ena_com_io_sq *io_sq)
|
||||
rc = ena_com_write_bounce_buffer_to_dev(io_sq,
|
||||
pkt_ctrl->curr_bounce_buf);
|
||||
if (unlikely(rc)) {
|
||||
ena_trc_err("failed to write bounce buffer to device\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to write bounce buffer to device\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -210,7 +216,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)
|
||||
rc = ena_com_write_bounce_buffer_to_dev(io_sq,
|
||||
pkt_ctrl->curr_bounce_buf);
|
||||
if (unlikely(rc)) {
|
||||
ena_trc_err("failed to write bounce buffer to device\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to write bounce buffer to device\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -280,7 +287,8 @@ static u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
|
||||
io_cq->cur_rx_pkt_cdesc_count = 0;
|
||||
io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;
|
||||
|
||||
ena_trc_dbg("ena q_id: %d packets were completed. first desc idx %u descs# %d\n",
|
||||
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"ENA q_id: %d packets were completed. first desc idx %u descs# %d\n",
|
||||
io_cq->qid, *first_cdesc_idx, count);
|
||||
} else {
|
||||
io_cq->cur_rx_pkt_cdesc_count += count;
|
||||
@ -296,6 +304,9 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
|
||||
struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
|
||||
|
||||
meta_desc = get_sq_desc(io_sq);
|
||||
if (unlikely(!meta_desc))
|
||||
return ENA_COM_FAULT;
|
||||
|
||||
memset(meta_desc, 0x0, sizeof(struct ena_eth_io_tx_meta_desc));
|
||||
|
||||
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
|
||||
@ -303,7 +314,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
|
||||
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
|
||||
|
||||
/* bits 0-9 of the mss */
|
||||
meta_desc->word2 |= (ena_meta->mss <<
|
||||
meta_desc->word2 |= ((u32)ena_meta->mss <<
|
||||
ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) &
|
||||
ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
|
||||
/* bits 10-13 of the mss */
|
||||
@ -313,7 +324,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
|
||||
|
||||
/* Extended meta desc */
|
||||
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
|
||||
meta_desc->len_ctrl |= (io_sq->phase <<
|
||||
meta_desc->len_ctrl |= ((u32)io_sq->phase <<
|
||||
ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) &
|
||||
ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
|
||||
|
||||
@ -326,7 +337,7 @@ static int ena_com_create_meta(struct ena_com_io_sq *io_sq,
|
||||
ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) &
|
||||
ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
|
||||
|
||||
meta_desc->word2 |= (ena_meta->l4_hdr_len <<
|
||||
meta_desc->word2 |= ((u32)ena_meta->l4_hdr_len <<
|
||||
ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) &
|
||||
ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
|
||||
|
||||
@ -348,20 +359,23 @@ static int ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
|
||||
|
||||
*have_meta = true;
|
||||
return ena_com_create_meta(io_sq, ena_meta);
|
||||
} else if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) {
|
||||
}
|
||||
|
||||
if (ena_com_meta_desc_changed(io_sq, ena_tx_ctx)) {
|
||||
*have_meta = true;
|
||||
/* Cache the meta desc */
|
||||
memcpy(&io_sq->cached_tx_meta, ena_meta,
|
||||
sizeof(struct ena_com_tx_meta));
|
||||
return ena_com_create_meta(io_sq, ena_meta);
|
||||
} else {
|
||||
*have_meta = false;
|
||||
return ENA_COM_OK;
|
||||
}
|
||||
|
||||
*have_meta = false;
|
||||
return ENA_COM_OK;
|
||||
}
|
||||
|
||||
static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
|
||||
struct ena_eth_io_rx_cdesc_base *cdesc)
|
||||
static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq,
|
||||
struct ena_com_rx_ctx *ena_rx_ctx,
|
||||
struct ena_eth_io_rx_cdesc_base *cdesc)
|
||||
{
|
||||
ena_rx_ctx->l3_proto = cdesc->status &
|
||||
ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
|
||||
@ -382,7 +396,8 @@ static void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
|
||||
(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >>
|
||||
ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
|
||||
|
||||
ena_trc_dbg("ena_rx_ctx->l3_proto %d ena_rx_ctx->l4_proto %d\nena_rx_ctx->l3_csum_err %d ena_rx_ctx->l4_csum_err %d\nhash frag %d frag: %d cdesc_status: %x\n",
|
||||
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n",
|
||||
ena_rx_ctx->l3_proto,
|
||||
ena_rx_ctx->l4_proto,
|
||||
ena_rx_ctx->l3_csum_err,
|
||||
@ -411,23 +426,26 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
u64 addr_hi;
|
||||
|
||||
ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX,
|
||||
"wrong Q type");
|
||||
ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type");
|
||||
|
||||
/* num_bufs +1 for potential meta desc */
|
||||
if (unlikely(!ena_com_sq_have_enough_space(io_sq, num_bufs + 1))) {
|
||||
ena_trc_dbg("Not enough space in the tx queue\n");
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Not enough space in the tx queue\n");
|
||||
return ENA_COM_NO_MEM;
|
||||
}
|
||||
|
||||
if (unlikely(header_len > io_sq->tx_max_header_size)) {
|
||||
ena_trc_err("header size is too large %d max header: %d\n",
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Header size is too large %d max header: %d\n",
|
||||
header_len, io_sq->tx_max_header_size);
|
||||
return ENA_COM_INVAL;
|
||||
}
|
||||
|
||||
if (unlikely(io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV
|
||||
&& !buffer_to_push)) {
|
||||
ena_trc_err("push header wasn't provided on LLQ mode\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Push header wasn't provided on LLQ mode\n");
|
||||
return ENA_COM_INVAL;
|
||||
}
|
||||
|
||||
@ -437,7 +455,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
|
||||
rc = ena_com_create_and_store_tx_meta_desc(io_sq, ena_tx_ctx, &have_meta);
|
||||
if (unlikely(rc)) {
|
||||
ena_trc_err("failed to create and store tx meta desc\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to create and store tx meta desc\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -445,7 +464,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
if (unlikely(!num_bufs && !header_len)) {
|
||||
rc = ena_com_close_bounce_buffer(io_sq);
|
||||
if (rc)
|
||||
ena_trc_err("failed to write buffers to LLQ\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to write buffers to LLQ\n");
|
||||
*nb_hw_desc = io_sq->tail - start_tail;
|
||||
return rc;
|
||||
}
|
||||
@ -459,16 +479,16 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
if (!have_meta)
|
||||
desc->len_ctrl |= ENA_ETH_IO_TX_DESC_FIRST_MASK;
|
||||
|
||||
desc->buff_addr_hi_hdr_sz |= (header_len <<
|
||||
desc->buff_addr_hi_hdr_sz |= ((u32)header_len <<
|
||||
ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) &
|
||||
ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
|
||||
desc->len_ctrl |= (io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
|
||||
desc->len_ctrl |= ((u32)io_sq->phase << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
|
||||
ENA_ETH_IO_TX_DESC_PHASE_MASK;
|
||||
|
||||
desc->len_ctrl |= ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
|
||||
|
||||
/* Bits 0-9 */
|
||||
desc->meta_ctrl |= (ena_tx_ctx->req_id <<
|
||||
desc->meta_ctrl |= ((u32)ena_tx_ctx->req_id <<
|
||||
ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) &
|
||||
ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
|
||||
|
||||
@ -506,7 +526,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
if (likely(i != 0)) {
|
||||
rc = ena_com_sq_update_tail(io_sq);
|
||||
if (unlikely(rc)) {
|
||||
ena_trc_err("failed to update sq tail\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to update sq tail\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -516,7 +537,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
|
||||
memset(desc, 0x0, sizeof(struct ena_eth_io_tx_desc));
|
||||
|
||||
desc->len_ctrl |= (io_sq->phase <<
|
||||
desc->len_ctrl |= ((u32)io_sq->phase <<
|
||||
ENA_ETH_IO_TX_DESC_PHASE_SHIFT) &
|
||||
ENA_ETH_IO_TX_DESC_PHASE_MASK;
|
||||
}
|
||||
@ -538,13 +559,15 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
|
||||
|
||||
rc = ena_com_sq_update_tail(io_sq);
|
||||
if (unlikely(rc)) {
|
||||
ena_trc_err("failed to update sq tail of the last descriptor\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed to update sq tail of the last descriptor\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = ena_com_close_bounce_buffer(io_sq);
|
||||
if (rc)
|
||||
ena_trc_err("failed when closing bounce buffer\n");
|
||||
ena_trc_err(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Failed when closing bounce buffer\n");
|
||||
|
||||
*nb_hw_desc = io_sq->tail - start_tail;
|
||||
return rc;
|
||||
@ -556,12 +579,13 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
|
||||
{
|
||||
struct ena_com_rx_buf_info *ena_buf = &ena_rx_ctx->ena_bufs[0];
|
||||
struct ena_eth_io_rx_cdesc_base *cdesc = NULL;
|
||||
u16 q_depth = io_cq->q_depth;
|
||||
u16 cdesc_idx = 0;
|
||||
u16 nb_hw_desc;
|
||||
u16 i = 0;
|
||||
|
||||
ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
|
||||
"wrong Q type");
|
||||
ena_com_io_cq_to_ena_dev(io_cq), "wrong Q type");
|
||||
|
||||
nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
|
||||
if (nb_hw_desc == 0) {
|
||||
@ -569,11 +593,13 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
|
||||
return 0;
|
||||
}
|
||||
|
||||
ena_trc_dbg("fetch rx packet: queue %d completed desc: %d\n",
|
||||
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"Fetch rx packet: queue %d completed desc: %d\n",
|
||||
io_cq->qid, nb_hw_desc);
|
||||
|
||||
if (unlikely(nb_hw_desc > ena_rx_ctx->max_bufs)) {
|
||||
ena_trc_err("Too many RX cdescs (%d) > MAX(%d)\n",
|
||||
ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"Too many RX cdescs (%d) > MAX(%d)\n",
|
||||
nb_hw_desc, ena_rx_ctx->max_bufs);
|
||||
return ENA_COM_NO_SPACE;
|
||||
}
|
||||
@ -582,21 +608,30 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
|
||||
ena_rx_ctx->pkt_offset = cdesc->offset;
|
||||
|
||||
do {
|
||||
ena_buf->len = cdesc->length;
|
||||
ena_buf->req_id = cdesc->req_id;
|
||||
ena_buf++;
|
||||
} while ((++i < nb_hw_desc) && (cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i)));
|
||||
ena_buf[i].len = cdesc->length;
|
||||
ena_buf[i].req_id = cdesc->req_id;
|
||||
if (unlikely(ena_buf[i].req_id >= q_depth))
|
||||
return ENA_COM_EIO;
|
||||
|
||||
if (++i >= nb_hw_desc)
|
||||
break;
|
||||
|
||||
cdesc = ena_com_rx_cdesc_idx_to_ptr(io_cq, cdesc_idx + i);
|
||||
|
||||
} while (1);
|
||||
|
||||
/* Update SQ head ptr */
|
||||
io_sq->next_to_comp += nb_hw_desc;
|
||||
|
||||
ena_trc_dbg("[%s][QID#%d] Updating SQ head to: %d\n", __func__,
|
||||
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"[%s][QID#%d] Updating SQ head to: %d\n", __func__,
|
||||
io_sq->qid, io_sq->next_to_comp);
|
||||
|
||||
/* Get rx flags from the last pkt */
|
||||
ena_com_rx_set_flags(ena_rx_ctx, cdesc);
|
||||
ena_com_rx_set_flags(io_cq, ena_rx_ctx, cdesc);
|
||||
|
||||
ena_rx_ctx->descs = nb_hw_desc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -607,7 +642,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
|
||||
struct ena_eth_io_rx_desc *desc;
|
||||
|
||||
ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
|
||||
"wrong Q type");
|
||||
ena_com_io_sq_to_ena_dev(io_sq), "wrong Q type");
|
||||
|
||||
if (unlikely(!ena_com_sq_have_enough_space(io_sq, 1)))
|
||||
return ENA_COM_NO_SPACE;
|
||||
@ -621,12 +656,16 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
|
||||
desc->length = ena_buf->len;
|
||||
|
||||
desc->ctrl = ENA_ETH_IO_RX_DESC_FIRST_MASK |
|
||||
ENA_ETH_IO_RX_DESC_LAST_MASK |
|
||||
(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK) |
|
||||
ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
|
||||
ENA_ETH_IO_RX_DESC_LAST_MASK |
|
||||
ENA_ETH_IO_RX_DESC_COMP_REQ_MASK |
|
||||
(io_sq->phase & ENA_ETH_IO_RX_DESC_PHASE_MASK);
|
||||
|
||||
desc->req_id = req_id;
|
||||
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"[%s] Adding single RX desc, Queue: %u, req_id: %u\n",
|
||||
__func__, io_sq->qid, req_id);
|
||||
|
||||
desc->buff_addr_lo = (u32)ena_buf->paddr;
|
||||
desc->buff_addr_hi =
|
||||
((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
@ -171,7 +171,8 @@ static inline bool ena_com_is_doorbell_needed(struct ena_com_io_sq *io_sq,
|
||||
llq_info->descs_per_entry);
|
||||
}
|
||||
|
||||
ena_trc_dbg("queue: %d num_descs: %d num_entries_needed: %d\n",
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Queue: %d num_descs: %d num_entries_needed: %d\n",
|
||||
io_sq->qid, num_descs, num_entries_needed);
|
||||
|
||||
return num_entries_needed > io_sq->entries_in_tx_burst_left;
|
||||
@ -182,14 +183,16 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
|
||||
u16 max_entries_in_tx_burst = io_sq->llq_info.max_entries_in_tx_burst;
|
||||
u16 tail = io_sq->tail;
|
||||
|
||||
ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Write submission queue doorbell for queue: %d tail: %d\n",
|
||||
io_sq->qid, tail);
|
||||
|
||||
ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
|
||||
|
||||
if (is_llq_max_tx_burst_exists(io_sq)) {
|
||||
ena_trc_dbg("reset available entries in tx burst for queue %d to %d\n",
|
||||
io_sq->qid, max_entries_in_tx_burst);
|
||||
ena_trc_dbg(ena_com_io_sq_to_ena_dev(io_sq),
|
||||
"Reset available entries in tx burst for queue %d to %d\n",
|
||||
io_sq->qid, max_entries_in_tx_burst);
|
||||
io_sq->entries_in_tx_burst_left = max_entries_in_tx_burst;
|
||||
}
|
||||
|
||||
@ -207,7 +210,8 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
|
||||
need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
|
||||
|
||||
if (unlikely(need_update)) {
|
||||
ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
|
||||
ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"Write completion queue doorbell for queue %d: head: %d\n",
|
||||
io_cq->qid, head);
|
||||
ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
|
||||
io_cq->last_head_update = head;
|
||||
@ -271,7 +275,8 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,
|
||||
|
||||
*req_id = READ_ONCE16(cdesc->req_id);
|
||||
if (unlikely(*req_id >= io_cq->q_depth)) {
|
||||
ena_trc_err("Invalid req id %d\n", cdesc->req_id);
|
||||
ena_trc_err(ena_com_io_cq_to_ena_dev(io_cq),
|
||||
"Invalid req id %d\n", cdesc->req_id);
|
||||
return ENA_COM_INVAL;
|
||||
}
|
||||
|
||||
|
||||
55
ena_plat.h
55
ena_plat.h
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
|
||||
* All rights reserved.
|
||||
@ -110,22 +110,33 @@ extern struct ena_bus_space ebs;
|
||||
|
||||
extern int ena_log_level;
|
||||
|
||||
#define ena_trace_raw(level, fmt, args...) \
|
||||
#define container_of(ptr, type, member) \
|
||||
({ \
|
||||
const __typeof(((type *)0)->member) *__p = (ptr); \
|
||||
(type *)((uintptr_t)__p - offsetof(type, member)); \
|
||||
})
|
||||
|
||||
#define ena_trace_raw(ctx, level, fmt, args...) \
|
||||
do { \
|
||||
((void)(ctx)); \
|
||||
if (((level) & ena_log_level) != (level)) \
|
||||
break; \
|
||||
printf(fmt, ##args); \
|
||||
} while (0)
|
||||
|
||||
#define ena_trace(level, fmt, args...) \
|
||||
ena_trace_raw(level, "%s() [TID:%d]: " \
|
||||
#define ena_trace(ctx, level, fmt, args...) \
|
||||
ena_trace_raw(ctx, level, "%s() [TID:%d]: " \
|
||||
fmt, __func__, curthread->td_tid, ##args)
|
||||
|
||||
|
||||
#define ena_trc_dbg(format, arg...) ena_trace(ENA_DBG, format, ##arg)
|
||||
#define ena_trc_info(format, arg...) ena_trace(ENA_INFO, format, ##arg)
|
||||
#define ena_trc_warn(format, arg...) ena_trace(ENA_WARNING, format, ##arg)
|
||||
#define ena_trc_err(format, arg...) ena_trace(ENA_ALERT, format, ##arg)
|
||||
#define ena_trc_dbg(ctx, format, arg...) \
|
||||
ena_trace(ctx, ENA_DBG, format, ##arg)
|
||||
#define ena_trc_info(ctx, format, arg...) \
|
||||
ena_trace(ctx, ENA_INFO, format, ##arg)
|
||||
#define ena_trc_warn(ctx, format, arg...) \
|
||||
ena_trace(ctx, ENA_WARNING, format, ##arg)
|
||||
#define ena_trc_err(ctx, format, arg...) \
|
||||
ena_trace(ctx, ENA_ALERT, format, ##arg)
|
||||
|
||||
#define unlikely(x) __predict_false(!!(x))
|
||||
#define likely(x) __predict_true(!!(x))
|
||||
@ -136,19 +147,10 @@ extern int ena_log_level;
|
||||
#define MAX_ERRNO 4095
|
||||
#define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO)
|
||||
|
||||
#define ENA_ASSERT(cond, format, arg...) \
|
||||
do { \
|
||||
if (unlikely(!(cond))) { \
|
||||
ena_trc_err( \
|
||||
"Assert failed on %s:%s:%d:" format, \
|
||||
__FILE__, __func__, __LINE__, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define ENA_WARN(cond, format, arg...) \
|
||||
#define ENA_WARN(cond, ctx, format, arg...) \
|
||||
do { \
|
||||
if (unlikely((cond))) { \
|
||||
ena_trc_warn(format, ##arg); \
|
||||
ena_trc_warn(ctx, format, ##arg); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
@ -187,6 +189,7 @@ static inline long PTR_ERR(const void *ptr)
|
||||
#define ENA_COM_NO_DEVICE ENODEV
|
||||
#define ENA_COM_PERMISSION EPERM
|
||||
#define ENA_COM_TIMER_EXPIRED ETIMEDOUT
|
||||
#define ENA_COM_EIO EIO
|
||||
|
||||
#define ENA_MSLEEP(x) pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0)
|
||||
#define ENA_USLEEP(x) pause_sbt("ena", SBT_1US * (x), SBT_1US, 0)
|
||||
@ -235,10 +238,17 @@ static inline long PTR_ERR(const void *ptr)
|
||||
cv_init(&((waitqueue).wq), "cv"); \
|
||||
mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF); \
|
||||
} while (0)
|
||||
#define ENA_WAIT_EVENT_DESTROY(waitqueue) \
|
||||
#define ENA_WAIT_EVENTS_DESTROY(admin_queue) \
|
||||
do { \
|
||||
cv_destroy(&((waitqueue).wq)); \
|
||||
mtx_destroy(&((waitqueue).mtx)); \
|
||||
struct ena_comp_ctx *comp_ctx; \
|
||||
int i; \
|
||||
for (i = 0; i < admin_queue->q_depth; i++) { \
|
||||
comp_ctx = get_comp_ctxt(admin_queue, i, false); \
|
||||
if (comp_ctx != NULL) { \
|
||||
cv_destroy(&((comp_ctx->wait_event).wq)); \
|
||||
mtx_destroy(&((comp_ctx->wait_event).mtx)); \
|
||||
} \
|
||||
} \
|
||||
} while (0)
|
||||
#define ENA_WAIT_EVENT_CLEAR(waitqueue) \
|
||||
cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description)
|
||||
@ -283,6 +293,7 @@ typedef uint32_t ena_atomic32_t;
|
||||
#define ENA_PRIu64 PRIu64
|
||||
|
||||
typedef uint64_t ena_time_t;
|
||||
typedef struct ifnet ena_netdev;
|
||||
|
||||
void ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg,
|
||||
int error);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user