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dts: Update our copy to be in sync with Linux 5.7

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MFC after:	2 months
This commit is contained in:
Emmanuel Vadot 2020-06-05 20:09:13 +00:00
commit 62352ec9fb
514 changed files with 20114 additions and 2833 deletions
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21
sys/gnu/dts/arm/am33xx-l4.dtsi
View File

@ -759,12 +759,27 @@
ranges = <0x0 0x200000 0x80000>;
};
target-module@300000 { /* 0x4a300000, ap 9 04.0 */
compatible = "ti,sysc";
status = "disabled";
pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x326000 0x4>,
<0x326004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_per 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x300000 0x80000>;
status = "disabled";
};
};
};

129
sys/gnu/dts/arm/am33xx.dtsi
View File

@ -47,6 +47,7 @@
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
enable-method = "ti,am3352";
device_type = "cpu";
reg = <0>;
@ -56,6 +57,17 @@
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
cpu-idle-states = <&mpu_gate>;
};
idle-states {
mpu_gate: mpu_gate {
compatible = "arm,idle-state";
entry-latency-us = <40>;
exit-latency-us = <90>;
min-residency-us = <300>;
ti,idle-wkup-m3;
};
};
};
@ -193,45 +205,100 @@
reg = <0x48200000 0x1000>;
};
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
target-module@49000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49000000 0x4>;
reg-names = "rev";
clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49000000 0x10000>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,edma-memcpy-channels = <20 21>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <20 21>;
};
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
target-module@49800000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49800000 0x4>,
<0x49800010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
target-module@49900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49900000 0x4>,
<0x49900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
target-module@49a00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49a00000 0x4>,
<0x49a00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@47810000 {

187
sys/gnu/dts/arm/am4372.dtsi
View File

@ -45,6 +45,7 @@
#size-cells = <0>;
cpu: cpu@0 {
compatible = "arm,cortex-a9";
enable-method = "ti,am4372";
device_type = "cpu";
reg = <0>;
@ -54,6 +55,17 @@
operating-points-v2 = <&cpu0_opp_table>;
clock-latency = <300000>; /* From omap-cpufreq driver */
cpu-idle-states = <&mpu_gate>;
};
idle-states {
mpu_gate: mpu_gate {
compatible = "arm,idle-state";
entry-latency-us = <40>;
exit-latency-us = <100>;
min-residency-us = <300>;
local-timer-stop;
};
};
};
@ -185,47 +197,102 @@
&pm_sram_data>;
};
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
target-module@49000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49000000 0x4>;
reg-names = "rev";
clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49000000 0x10000>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,edma-memcpy-channels = <58 59>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <58 59>;
};
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
target-module@49800000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49800000 0x4>,
<0x49800010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
target-module@49900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49900000 0x4>,
<0x49900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
target-module@49a00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49a00000 0x4>,
<0x49a00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@47810000 {
@ -344,6 +411,28 @@
};
};
pruss_tm: target-module@54400000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x54426000 0x4>,
<0x54426004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_per 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54400000 0x80000>;
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
@ -394,38 +483,6 @@
};
};
dss: dss@4832a000 {
compatible = "ti,omap3-dss";
reg = <0x4832a000 0x200>;
status = "disabled";
ti,hwmods = "dss_core";
clocks = <&disp_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dispc: dispc@4832a400 {
compatible = "ti,omap3-dispc";
reg = <0x4832a400 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&disp_clk>;
clock-names = "fck";
max-memory-bandwidth = <230000000>;
};
rfbi: rfbi@4832a800 {
compatible = "ti,omap3-rfbi";
reg = <0x4832a800 0x100>;
ti,hwmods = "dss_rfbi";
clocks = <&disp_clk>;
clock-names = "fck";
status = "disabled";
};
};
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x40000>; /* 256k */

2
sys/gnu/dts/arm/am437x-gp-evm.dts
View File

@ -943,7 +943,7 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
};
&elm {

2
sys/gnu/dts/arm/am437x-idk-evm.dts
View File

@ -504,7 +504,7 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
};
&rtc {

77
sys/gnu/dts/arm/am437x-l4.dtsi
View File

@ -2117,7 +2117,6 @@
target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dss_core";
reg = <0x2a000 0x4>,
<0x2a010 0x4>,
<0x2a014 0x4>;
@ -2135,6 +2134,82 @@
<0x00000800 0x0002a800 0x00000400>,
<0x00000c00 0x0002ac00 0x00000400>,
<0x00001000 0x0002b000 0x00001000>;
dss: dss@0 {
compatible = "ti,omap3-dss";
reg = <0 0x200>;
status = "disabled";
clocks = <&disp_clk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x00000400>,
<0x00000400 0x00000400 0x00000400>,
<0x00000800 0x00000800 0x00000400>,
<0x00000c00 0x00000c00 0x00000400>,
<0x00001000 0x00001000 0x00001000>;
target-module@400 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x400 0x4>,
<0x410 0x4>,
<0x414 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x400>;
dispc: dispc@0 {
compatible = "ti,omap3-dispc";
reg = <0 0x400>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&disp_clk>;
clock-names = "fck";
max-memory-bandwidth = <230000000>;
};
};
target-module@800 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x800 0x4>,
<0x810 0x4>,
<0x814 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x400>;
rfbi: rfbi@0 {
compatible = "ti,omap3-rfbi";
reg = <0 0x100>;
clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
clock-names = "fck";
status = "disabled";
};
};
};
};
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */

4
sys/gnu/dts/arm/am437x-sk-evm.dts
View File

@ -833,13 +833,13 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

50
sys/gnu/dts/arm/am57-pruss.dtsi Normal file
View File

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
*
* Common PRUSS data for TI AM57xx platforms
*/
&ocp {
pruss1_tm: target-module@4b226000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x4b226000 0x4>,
<0x4b226004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4b200000 0x80000>;
};
pruss2_tm: target-module@4b2a6000 {
compatible = "ti,sysc-pruss", "ti,sysc";
reg = <0x4b2a6000 0x4>,
<0x4b2a6004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
SYSC_PRUSS_SUB_MWAIT)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4b280000 0x80000>;
};
};

1
sys/gnu/dts/arm/am5718.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "dra72x.dtsi"
#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5718", "ti,dra7";

4
sys/gnu/dts/arm/am571x-idk.dts
View File

@ -190,13 +190,13 @@
&cpsw_port1 {
phy-handle = <&ethphy0_sw>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
ti,dual-emac-pvid = <1>;
};
&cpsw_port2 {
phy-handle = <&ethphy1_sw>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
ti,dual-emac-pvid = <2>;
};

1
sys/gnu/dts/arm/am5728.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "dra74x.dtsi"
#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5728", "ti,dra7";

1
sys/gnu/dts/arm/am5748.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "dra76x.dtsi"
#include "am57-pruss.dtsi"
/ {
compatible = "ti,am5748", "ti,dra762", "ti,dra7";

4
sys/gnu/dts/arm/am574x-idk.dts
View File

@ -40,3 +40,7 @@
status = "okay";
dual_emac;
};
&m_can0 {
status = "disabled";
};

4
sys/gnu/dts/arm/am57xx-beagle-x15-common.dtsi
View File

@ -433,13 +433,13 @@
&cpsw_emac0 {
phy-handle = <&phy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

4
sys/gnu/dts/arm/am57xx-idk-common.dtsi
View File

@ -408,13 +408,13 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-rxid";
dual_emac_res_vlan = <2>;
};

2
sys/gnu/dts/arm/arm-realview-pbx.dtsi
View File

@ -210,7 +210,7 @@
};
};
soc: soc@0 {
soc: soc {
compatible = "arm,realview-pbx-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
sys/gnu/dts/arm/aspeed-g4.dtsi
View File

@ -164,6 +164,8 @@
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <5>;
aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2d_default>;
status = "disabled";

2
sys/gnu/dts/arm/aspeed-g5.dtsi
View File

@ -195,6 +195,8 @@
reg = <0x1e6a0000 0x300>;
interrupts = <5>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <5>;
aspeed,vhub-generic-endpoints = <15>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled";

25
sys/gnu/dts/arm/aspeed-g6-pinctrl.dtsi
View File

@ -1112,6 +1112,31 @@
groups = "UART9";
};
pinctrl_usb2ah_default: usb2ah_default {
function = "USB2AH";
groups = "USBA";
};
pinctrl_usb2ad_default: usb2ad_default {
function = "USB2AD";
groups = "USBA";
};
pinctrl_usb2bh_default: usb2bh_default {
function = "USB2BH";
groups = "USBB";
};
pinctrl_usb2bd_default: usb2bd_default {
function = "USB2BD";
groups = "USBB";
};
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USBB";
};
pinctrl_vb_default: vb_default {
function = "VB";
groups = "VB";

45
sys/gnu/dts/arm/aspeed-g6.dtsi
View File

@ -245,6 +245,51 @@
status = "disabled";
};
ehci0: usb@1e6a1000 {
compatible = "aspeed,ast2600-ehci", "generic-ehci";
reg = <0x1e6a1000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ah_default>;
status = "disabled";
};
ehci1: usb@1e6a3000 {
compatible = "aspeed,ast2600-ehci", "generic-ehci";
reg = <0x1e6a3000 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2bh_default>;
status = "disabled";
};
uhci: usb@1e6b0000 {
compatible = "aspeed,ast2600-uhci", "generic-uhci";
reg = <0x1e6b0000 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#ports = <2>;
clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
status = "disabled";
/*
* No default pinmux, it will follow EHCI, use an
* explicit pinmux override if EHCI is not enabled.
*/
};
vhub: usb-vhub@1e6a0000 {
compatible = "aspeed,ast2600-usb-vhub";
reg = <0x1e6a0000 0x350>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
aspeed,vhub-downstream-ports = <7>;
aspeed,vhub-generic-endpoints = <21>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2ad_default>;
status = "disabled";
};
apb {
compatible = "simple-bus";
#address-cells = <1>;

2
sys/gnu/dts/arm/at91-dvk_su60_somc_lcm.dtsi
View File

@ -17,7 +17,7 @@
};
panel: panel {
compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92", "simple-panel";
compatible = "winstar,wf70gtiagdng0", "innolux,at070tn92";
backlight = <&backlight>;
power-supply = <&vcc_lcd_reg>;
#address-cells = <1>;

5
sys/gnu/dts/arm/at91-sam9x60ek.dts
View File

@ -645,3 +645,8 @@
&usb2 {
status = "okay";
};
&watchdog {
status = "okay";
};

12
sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts
View File

@ -186,6 +186,11 @@
pinmux = <PIN_PA10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA16__GPIO>;
bias-disable;
};
};
&pwm0 {
@ -248,6 +253,13 @@
status = "okay";
};
&usb0 {
atmel,vbus-gpio = <&pioA PIN_PA16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0

33
sys/gnu/dts/arm/at91-sama5d2_ptc_ek.dts
View File

@ -180,8 +180,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -198,8 +201,11 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_flx0_default>;
pinctrl-1 = <&pinctrl_flx0_gpio>;
sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>;
atmel,fifo-size = <16>;
status = "okay";
};
@ -226,8 +232,11 @@
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PC7 GPIO_ACTIVE_HIGH>;
status = "okay";
at24@50 {
@ -244,18 +253,36 @@
bias-disable;
};
pinctrl_flx0_gpio: flx0_gpio {
pinmux = <PIN_PB28__GPIO>,
<PIN_PB29__GPIO>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PC6__TWD1>,
<PIN_PC7__TWCK1>;
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PC6__GPIO>,
<PIN_PC7__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PA10__GPIO>;
bias-pull-up;

33
sys/gnu/dts/arm/at91-sama5d2_xplained.dts
View File

@ -129,8 +129,11 @@
i2c0: i2c@f8028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>;
i2c-sda-hold-time-ns = <350>;
status = "okay";
@ -331,8 +334,11 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_flx4_default>;
pinctrl-1 = <&pinctrl_flx4_gpio>;
sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
@ -343,11 +349,14 @@
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD5 GPIO_ACTIVE_HIGH>;
status = "okay";
at24@54 {
@ -441,18 +450,36 @@
bias-disable;
};
pinctrl_flx4_gpio: flx4_gpio {
pinmux = <PIN_PD12__GPIO>,
<PIN_PD13__GPIO>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinctrl_i2s0_default: i2s0_default {
pinmux = <PIN_PC1__I2SC0_CK>,
<PIN_PC2__I2SC0_MCK>,

2
sys/gnu/dts/arm/at91-sama5d4_ma5d4evk.dts
View File

@ -136,7 +136,7 @@
panel: panel {
/* Actually Ampire 800480R2 */
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
compatible = "foxlink,fl500wvr00-a0t";
backlight = <&backlight>;
#address-cells = <1>;
#size-cells = <0>;

2
sys/gnu/dts/arm/at91sam9n12ek.dts
View File

@ -238,7 +238,7 @@
};
panel: panel {
compatible = "qiaodian,qd43003c0-40", "simple-panel";
compatible = "qiaodian,qd43003c0-40";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;

2
sys/gnu/dts/arm/at91sam9x5dm.dtsi
View File

@ -27,7 +27,7 @@
};
panel: panel {
compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
compatible = "foxlink,fl500wvr00-a0t";
backlight = <&backlight>;
power-supply = <&panel_reg>;
#address-cells = <1>;

6
sys/gnu/dts/arm/bcm-hr2.dtsi
View File

@ -75,7 +75,7 @@
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};
@ -83,7 +83,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0x20600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
@ -91,7 +91,7 @@
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x20620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};

74
sys/gnu/dts/arm/bcm2711-rpi-4-b.dts
View File

@ -20,6 +20,7 @@
};
aliases {
emmc2bus = &emmc2bus;
ethernet0 = &genet;
pcie0 = &pcie0;
};
@ -74,6 +75,79 @@
};
};
&gpio {
/*
* Parts taken from rpi_SCH_4b_4p0_reduced.pdf and
* the official GPU firmware DT blob.
*
* Legend:
* "FOO" = GPIO line named "FOO" on the schematic
* "FOO_N" = GPIO line named "FOO" on schematic, active low
*/
gpio-line-names = "ID_SDA",
"ID_SCL",
"SDA1",
"SCL1",
"GPIO_GCLK",
"GPIO5",
"GPIO6",
"SPI_CE1_N",
"SPI_CE0_N",
"SPI_MISO",
"SPI_MOSI",
"SPI_SCLK",
"GPIO12",
"GPIO13",
/* Serial port */
"TXD1",
"RXD1",
"GPIO16",
"GPIO17",
"GPIO18",
"GPIO19",
"GPIO20",
"GPIO21",
"GPIO22",
"GPIO23",
"GPIO24",
"GPIO25",
"GPIO26",
"GPIO27",
"RGMII_MDIO",
"RGMIO_MDC",
/* Used by BT module */
"CTS0",
"RTS0",
"TXD0",
"RXD0",
/* Used by Wifi */
"SD1_CLK",
"SD1_CMD",
"SD1_DATA0",
"SD1_DATA1",
"SD1_DATA2",
"SD1_DATA3",
/* Shared with SPI flash */
"PWM0_MISO",
"PWM1_MOSI",
"STATUS_LED_G_CLK",
"SPIFLASH_CE_N",
"SDA0",
"SCL0",
"RGMII_RXCLK",
"RGMII_RXCTL",
"RGMII_RXD0",
"RGMII_RXD1",
"RGMII_RXD2",
"RGMII_RXD3",
"RGMII_TXCLK",
"RGMII_TXCTL",
"RGMII_TXD0",
"RGMII_TXD1",
"RGMII_TXD2",
"RGMII_TXD3";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;

25
sys/gnu/dts/arm/bcm2711.dtsi
View File

@ -241,17 +241,32 @@
status = "disabled";
};
hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
};
/*
* emmc2 has different DMA constraints based on SoC revisions. It was
* moved into its own bus, so as for RPi4's firmware to update them.
* The firmware will find whether the emmc2bus alias is defined, and if
* so, it'll edit the dma-ranges property below accordingly.
*/
emmc2bus: emmc2bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
emmc2: emmc2@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x7e340000 0x100>;
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2711_CLOCK_EMMC2>;
status = "disabled";
};
hvs@7e400000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
};
};
arm-pmu {

2
sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
View File

@ -24,7 +24,7 @@
leds {
act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};

3
sys/gnu/dts/arm/bcm2835-rpi.dtsi
View File

@ -14,6 +14,9 @@
soc {
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
mboxes = <&mailbox>;
dma-ranges;
};

1
sys/gnu/dts/arm/bcm283x.dtsi
View File

@ -372,6 +372,7 @@
"dsi0_ddr2",
"dsi0_ddr";
status = "disabled";
};
aux: aux@7e215000 {

14
sys/gnu/dts/arm/dm814x-clocks.dtsi
View File

@ -362,4 +362,18 @@
#clock-cells = <2>;
};
};
alwon_ethernet_cm: alwon_ethernet_cm@15d4 {
compatible = "ti,omap4-cm";
reg = <0x15d4 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x15d4 0x4>;
alwon_ethernet_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0 0x4>;
#clock-cells = <2>;
};
};
};

254
sys/gnu/dts/arm/dm814x.dtsi
View File

@ -4,6 +4,8 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm814.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/dm814x.h>
@ -519,53 +521,123 @@
reg = <0x47810000 0x1000>;
};
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
target-module@49000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49000000 0x4>;
reg-names = "rev";
clocks = <&alwon_clkctrl DM814_TPCC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49000000 0x10000>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 3>, <&edma_tptc3 0>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,edma-memcpy-channels = <20 21>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 3>, <&edma_tptc3 0>;
ti,edma-memcpy-channels = <20 21>;
};
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
target-module@49800000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49800000 0x4>,
<0x49800010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
target-module@49900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49900000 0x4>,
<0x49900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
target-module@49a00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49a00000 0x4>,
<0x49a00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc3: tptc@49b00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc3";
reg = <0x49b00000 0x100000>;
interrupts = <115>;
interrupt-names = "edma3_tcerrint";
target-module@49b00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49b00000 0x4>,
<0x49b00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM814_TPTC3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49b00000 0x100000>;
edma_tptc3: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <115>;
interrupt-names = "edma3_tcerrint";
};
};
/* See TRM "Table 1-318. L4HS Instance Summary" */
@ -574,57 +646,73 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x1b4040>;
};
/* REVISIT: Move to live under l4hs once driver is fixed */
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0x4a100000 0x800
0x4a100900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a100800 {
compatible = "ti,davinci_mdio";
target-module@100000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
reg = <0x100900 0x4>,
<0x100908 0x4>,
<0x100904 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <0>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,syss-mask = <1>;
clocks = <&alwon_ethernet_clkctrl DM814_ETHERNET_CPGMAC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
bus_freq = <1000000>;
reg = <0x4a100800 0x100>;
};
#size-cells = <1>;
ranges = <0 0x100000 0x8000>;
cpsw_emac0: slave@4a100200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1>;
mac: ethernet@0 {
compatible = "ti,cpsw";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
reg = <0 0x800>,
<0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
/*
* c0_rx_thresh_pend
* c0_rx_pend
* c0_tx_pend
* c0_misc_pend
*/
interrupts = <40 41 42 43>;
ranges = <0 0 0x8000>;
syscon = <&scm_conf>;
};
davinci_mdio: mdio@800 {
compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
clocks = <&cpsw_125mhz_gclk>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
reg = <0x800 0x100>;
};
cpsw_emac1: slave@4a100300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2>;
cpsw_emac0: slave@200 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 1>;
};
cpsw_emac1: slave@300 {
/* Filled in by U-Boot */
mac-address = [ 00 00 00 00 00 00 ];
phys = <&phy_gmii_sel 2>;
};
};
};
};

148
sys/gnu/dts/arm/dm816x.dtsi
View File

@ -4,6 +4,8 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/dm816.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/omap.h>
@ -138,13 +140,123 @@
};
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x40>;
interrupts = <12 13 14>;
#dma-cells = <1>;
target-module@49000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49000000 0x4>;
reg-names = "rev";
clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49000000 0x10000>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 3>, <&edma_tptc3 0>;
ti,edma-memcpy-channels = <20 21>;
};
};
target-module@49800000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49800000 0x4>,
<0x49800010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49800000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49900000 0x4>,
<0x49900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49900000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49a00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49a00000 0x4>,
<0x49a00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49a00000 0x100000>;
edma_tptc2: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
};
target-module@49b00000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x49b00000 0x4>,
<0x49b00010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_SMART>;
clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x49b00000 0x100000>;
edma_tptc3: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <115>;
interrupt-names = "edma3_tcerrint";
};
};
elm: elm@48080000 {
@ -185,7 +297,7 @@
#address-cells = <2>;
#size-cells = <1>;
interrupts = <100>;
dmas = <&edma 52>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>;
@ -202,7 +314,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
dmas = <&edma 58 &edma 59>;
dmas = <&edma 58 0 &edma 59 0>;
dma-names = "tx", "rx";
};
@ -213,7 +325,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
dmas = <&edma 60 &edma 61>;
dmas = <&edma 60 0 &edma 61 0>;
dma-names = "tx", "rx";
};
@ -311,10 +423,10 @@
interrupts = <65>;
ti,spi-num-cs = <4>;
ti,hwmods = "mcspi1";
dmas = <&edma 16 &edma 17
&edma 18 &edma 19
&edma 20 &edma 21
&edma 22 &edma 23>;
dmas = <&edma 16 0 &edma 17 0
&edma 18 0 &edma 19 0
&edma 20 0 &edma 21 0
&edma 22 0 &edma 23 0>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
@ -324,7 +436,7 @@
reg = <0x48060000 0x11000>;
ti,hwmods = "mmc1";
interrupts = <64>;
dmas = <&edma 24 &edma 25>;
dmas = <&edma 24 0 &edma 25 0>;
dma-names = "tx", "rx";
};
@ -392,7 +504,7 @@
reg = <0x48020000 0x2000>;
clock-frequency = <48000000>;
interrupts = <72>;
dmas = <&edma 26 &edma 27>;
dmas = <&edma 26 0 &edma 27 0>;
dma-names = "tx", "rx";
};
@ -402,7 +514,7 @@
reg = <0x48022000 0x2000>;
clock-frequency = <48000000>;
interrupts = <73>;
dmas = <&edma 28 &edma 29>;
dmas = <&edma 28 0 &edma 29 0>;
dma-names = "tx", "rx";
};
@ -412,7 +524,7 @@
reg = <0x48024000 0x2000>;
clock-frequency = <48000000>;
interrupts = <74>;
dmas = <&edma 30 &edma 31>;
dmas = <&edma 30 0 &edma 31 0>;
dma-names = "tx", "rx";
};

6
sys/gnu/dts/arm/dra62x.dtsi
View File

@ -12,12 +12,12 @@
/* Compared to dm814x, dra62x has different offsets for Ethernet */
&mac {
reg = <0x4a100000 0x800
0x4a101200 0x100>;
reg = <0 0x800>,
<0x1200 0x100>;
};
&davinci_mdio {
reg = <0x4a101000 0x100>;
reg = <0x1000 0x100>;
};
#include "dra62x-clocks.dtsi"

221
sys/gnu/dts/arm/dra7.dtsi
View File

@ -143,7 +143,7 @@
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
ocp: ocp {
compatible = "ti,dra7-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -172,6 +172,7 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
dma-ranges;
/**
* To enable PCI endpoint mode, disable the pcie1_rc
* node and enable pcie1_ep mode.
@ -185,7 +186,6 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -230,6 +230,7 @@
#address-cells = <1>;
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
dma-ranges;
status = "disabled";
pcie2_rc: pcie@51800000 {
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
@ -240,7 +241,6 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -334,43 +334,73 @@
#pinctrl-cells = <2>;
};
edma: edma@43300000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x43300000 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
target-module@43300000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x43300000 0x4>;
reg-names = "rev";
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43300000 0x100000>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
edma: dma@0 {
compatible = "ti,edma3-tpcc";
reg = <0 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
};
};
edma_tptc0: tptc@43400000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x43400000 0x100000>;
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
target-module@43400000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x43400000 0x4>;
reg-names = "rev";
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43400000 0x100000>;
edma_tptc0: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
};
edma_tptc1: tptc@43500000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x43500000 0x100000>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
target-module@43500000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x43500000 0x4>;
reg-names = "rev";
clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43500000 0x100000>;
edma_tptc1: dma@0 {
compatible = "ti,edma3-tptc";
reg = <0 0x100000>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
};
dmm@4e000000 {
@ -708,44 +738,99 @@
ti,irqs-safe-map = <0>;
};
dss: dss@58000000 {
compatible = "ti,dra7-dss";
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
status = "disabled";
ti,hwmods = "dss_core";
/* CTRL_CORE_DSS_PLL_CONTROL */
syscon-pll-ctrl = <&scm_conf 0x538>;
target-module@58000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000000 4>,
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ranges = <0 0x58000000 0x800000>;
dispc@58001000 {
compatible = "ti,dra7-dispc";
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
};
hdmi: encoder@58060000 {
compatible = "ti,dra7-hdmi";
reg = <0x58040000 0x200>,
<0x58040200 0x80>,
<0x58040300 0x80>,
<0x58060000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
dss: dss@0 {
compatible = "ti,dra7-dss";
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
status = "disabled";
ti,hwmods = "dss_hdmi";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma_xbar 76>;
dma-names = "audio_tx";
/* CTRL_CORE_DSS_PLL_CONTROL */
syscon-pll-ctrl = <&scm_conf 0x538>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x800000>;
target-module@1000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x1000 0x4>,
<0x1010 0x4>,
<0x1014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x1000>;
dispc@0 {
compatible = "ti,dra7-dispc";
reg = <0 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
};
};
target-module@40000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000 0x40000>;
hdmi: encoder@0 {
compatible = "ti,dra7-hdmi";
reg = <0 0x200>,
<0x200 0x80>,
<0x300 0x80>,
<0x20000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma_xbar 76>;
dma-names = "audio_tx";
};
};
};
};

6
sys/gnu/dts/arm/dra72x.dtsi
View File

@ -60,9 +60,9 @@
};
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004300 0x20>;
reg = <0 0x80>,
<0x4054 0x4>,
<0x4300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,

10
sys/gnu/dts/arm/dra74x.dtsi
View File

@ -132,11 +132,11 @@
};
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,
<0x58004300 0x20>,
<0x58009054 0x4>,
<0x58009300 0x20>;
reg = <0 0x80>,
<0x4054 0x4>,
<0x4300 0x20>,
<0x9054 0x4>,
<0x9300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";

6
sys/gnu/dts/arm/ecx-2000.dts
View File

@ -13,7 +13,6 @@
compatible = "calxeda,ecx-2000";
#address-cells = <2>;
#size-cells = <2>;
clock-ranges;
cpus {
#address-cells = <1>;
@ -83,8 +82,7 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
#address-cells = <1>;
#address-cells = <0>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xfff11000 0x1000>,
@ -95,7 +93,7 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
};
};

17
sys/gnu/dts/arm/ecx-common.dtsi
View File

@ -27,10 +27,11 @@
reg = <0xffe08000 0x10000>;
interrupts = <0 83 4>;
dma-coherent;
calxeda,port-phys = <&combophy5 0 &combophy0 0
&combophy0 1 &combophy0 2
&combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
<&combophy0 1>, <&combophy0 2>,
<&combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
<&gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
};
@ -114,8 +115,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0xfff36000 0x1000>;
interrupts = <0 20 4>;
clocks = <&pclk>;
clock-names = "apb_pclk";
clocks = <&pclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
smic@fff3a000 {
@ -202,14 +203,14 @@
ethernet@fff50000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff50000 0x1000>;
interrupts = <0 77 4 0 78 4 0 79 4>;
interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
dma-coherent;
};
ethernet@fff51000 {
compatible = "calxeda,hb-xgmac";
reg = <0xfff51000 0x1000>;
interrupts = <0 80 4 0 81 4 0 82 4>;
interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
dma-coherent;
};

2
sys/gnu/dts/arm/exynos3250-artik5.dtsi
View File

@ -23,7 +23,7 @@
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x1ff00000>;
reg = <0x40000000 0x1f800000>;
};
firmware@205f000 {

4
sys/gnu/dts/arm/exynos4210-universal_c210.dts
View File

@ -115,7 +115,7 @@
gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
cs-gpios = <&gpy4 3 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>;
lcd@0 {
compatible = "samsung,ld9040";
@ -124,8 +124,6 @@
vci-supply = <&ldo17_reg>;
reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <1200000>;
spi-cpol;
spi-cpha;
power-on-delay = <10>;
reset-delay = <10>;
panel-width-mm = <90>;

9
sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
View File

@ -165,6 +165,15 @@
cpu0-supply = <&buck2_reg>;
};
&cpu0_opp_table {
opp-1000000000 {
opp-suspend;
};
opp-800000000 {
/delete-property/opp-suspend;
};
};
&pinctrl_1 {
gpio_power_key: power_key {
samsung,pins = "gpx1-3";

10
sys/gnu/dts/arm/exynos5250-arndale.dts
View File

@ -93,22 +93,23 @@
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "MAIN_DC";
regulator-always-on;
};
mmc_reg: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "VDD_33ON_2.8V";
regulator-name = "VDD_MMC";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_hdmi_en: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "hdmi-en";
regulator-always-on;
};
vcc_1v2_reg: regulator@3 {
@ -117,6 +118,7 @@
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_1v8_reg: regulator@4 {
@ -125,6 +127,7 @@
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vcc_3v3_reg: regulator@5 {
@ -133,6 +136,7 @@
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};

2
sys/gnu/dts/arm/exynos5420-arndale-octa.dts
View File

@ -584,6 +584,7 @@
regulator-name = "PVDD_G3DS_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
@ -697,6 +698,7 @@
regulator-name = "PVDD_G3D_1V0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;

8
sys/gnu/dts/arm/exynos5422-cpus.dtsi
View File

@ -31,6 +31,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
dynamic-power-coefficient = <90>;
};
cpu1: cpu@101 {
@ -43,6 +44,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
dynamic-power-coefficient = <90>;
};
cpu2: cpu@102 {
@ -55,6 +57,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
dynamic-power-coefficient = <90>;
};
cpu3: cpu@103 {
@ -67,6 +70,7 @@
operating-points-v2 = <&cluster_a7_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <539>;
dynamic-power-coefficient = <90>;
};
cpu4: cpu@0 {
@ -79,6 +83,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <310>;
};
cpu5: cpu@1 {
@ -91,6 +96,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <310>;
};
cpu6: cpu@2 {
@ -103,6 +109,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <310>;
};
cpu7: cpu@3 {
@ -115,6 +122,7 @@
operating-points-v2 = <&cluster_a15_opp_table>;
#cooling-cells = <2>; /* min followed by max */
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <310>;
};
};
};

1
sys/gnu/dts/arm/exynos5422-odroid-core.dtsi
View File

@ -901,6 +901,7 @@
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;

30
sys/gnu/dts/arm/exynos5422-odroidhc1.dts
View File

@ -215,6 +215,36 @@
};
};
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu 0>;
trips {
gpu_alert0: gpu-alert-0 {
temperature = <70000>;
hysteresis = <10000>;
type = "active";
};
gpu_alert1: gpu-alert-1 {
temperature = <85000>;
hysteresis = <10000>;
type = "active";
};
gpu_crit0: gpu-crit-0 {
temperature = <120000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&gpu 0 2>;
};
map1 {
trip = <&gpu_alert1>;
cooling-device = <&gpu 3 6>;
};
};
};
};
};

59
sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
View File

@ -357,6 +357,65 @@
};
};
};
gpu_thermal: gpu-thermal {
thermal-sensors = <&tmu_gpu 0>;
polling-delay-passive = <250>;
polling-delay = <0>;
trips {
gpu_alert0: gpu-alert-0 {
temperature = <50000>;
hysteresis = <5000>;
type = "active";
};
gpu_alert1: gpu-alert-1 {
temperature = <60000>;
hysteresis = <5000>;
type = "active";
};
gpu_alert2: gpu-alert-2 {
temperature = <70000>;
hysteresis = <5000>;
type = "active";
};
gpu_crit0: gpu-crit-0 {
temperature = <120000>;
hysteresis = <0>;
type = "critical";
};
gpu_alert3: gpu-alert-3 {
temperature = <70000>;
hysteresis = <10000>;
type = "passive";
};
gpu_alert4: gpu-alert-4 {
temperature = <85000>;
hysteresis = <10000>;
type = "passive";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&fan0 0 1>;
};
map1 {
trip = <&gpu_alert1>;
cooling-device = <&fan0 1 2>;
};
map2 {
trip = <&gpu_alert2>;
cooling-device = <&fan0 2 3>;
};
map3 {
trip = <&gpu_alert3>;
cooling-device = <&gpu 0 2>;
};
map4 {
trip = <&gpu_alert4>;
cooling-device = <&gpu 3 6>;
};
};
};
};
};

50
sys/gnu/dts/arm/gemini-dlink-dir-685.dts
View File

@ -119,13 +119,11 @@
/*
* This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
* Since the platform has no temperature sensor, this is controlled
* from userspace by using the hard disks S.M.A.R.T. temperature
* sensor. It is turned on when the temperature exceeds 46 degrees
* and turned off when the temperatures goes below 41 degrees
* (celsius).
*/
gpio-fan {
fan0: gpio-fan {
compatible = "gpio-fan";
/* Collides with IDE */
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
@ -133,6 +131,40 @@
#cooling-cells = <2>;
};
thermal-zones {
chassis-thermal {
/* Poll every 20 seconds */
polling-delay = <20000>;
/* Poll every 2nd second when cooling */
polling-delay-passive = <2000>;
/* Use the thermal sensor in the hard drive */
thermal-sensors = <&drive0>;
/* Tripping points from the fan.script in the rootfs */
trips {
alert: chassis-alert {
/* At 43 degrees turn on the fan */
temperature = <43000>;
hysteresis = <3000>;
type = "active";
};
crit: chassis-crit {
/* Just shut down at 60 degrees */
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&alert>;
cooling-device = <&fan0 1 1>;
};
};
};
};
/*
* The touchpad input is connected to a GPIO bit-banged
* I2C bus.
@ -443,8 +475,18 @@
};
};
ata@63000000 {
ide@63000000 {
status = "okay";
/*
* This drive may have a temperature sensor with a
* thermal zone we can use for thermal control of the
* chassis temperature using the fan.
*/
drive0: ide-port@0 {
reg = <0>;
#thermal-sensor-cells = <0>;
};
};
display-controller@6a000000 {

2
sys/gnu/dts/arm/gemini-dlink-dns-313.dts
View File

@ -297,7 +297,7 @@
};
};
ata@63000000 {
ide@63000000 {
status = "okay";
};
};

4
sys/gnu/dts/arm/gemini-nas4220b.dts
View File

@ -170,11 +170,11 @@
};
};
ata@63000000 {
ide@63000000 {
status = "okay";
};
ata@63400000 {
ide@63400000 {
status = "okay";
};

4
sys/gnu/dts/arm/gemini-sl93512r.dts
View File

@ -293,11 +293,11 @@
};
};
ata@63000000 {
ide@63000000 {
status = "okay";
};
ata@63400000 {
ide@63400000 {
status = "okay";
};

2
sys/gnu/dts/arm/gemini-sq201.dts
View File

@ -289,7 +289,7 @@
};
};
ata@63000000 {
ide@63000000 {
status = "okay";
};

8
sys/gnu/dts/arm/gemini.dtsi
View File

@ -356,7 +356,7 @@
};
};
ata@63000000 {
ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
@ -365,9 +365,11 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ata@63400000 {
ide@63400000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63400000 0x1000>;
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
@ -376,6 +378,8 @@
clock-names = "PCLK";
sata = <&sata>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
dma-controller@67000000 {

11
sys/gnu/dts/arm/highbank.dts
View File

@ -13,7 +13,6 @@
compatible = "calxeda,highbank";
#address-cells = <1>;
#size-cells = <1>;
clock-ranges;
cpus {
#address-cells = <1>;
@ -96,7 +95,7 @@
};
};
memory {
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x00000000 0xff900000>;
@ -128,14 +127,12 @@
intc: interrupt-controller@fff11000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
#address-cells = <1>;
interrupt-controller;
reg = <0xfff11000 0x1000>,
<0xfff10100 0x100>;
};
L2: l2-cache {
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xfff12000 0x1000>;
interrupts = <0 70 4>;
@ -145,14 +142,14 @@
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
};
sregs@fff3c200 {
compatible = "calxeda,hb-sregs-l2-ecc";
reg = <0xfff3c200 0x100>;
interrupts = <0 71 4 0 72 4>;
interrupts = <0 71 4>, <0 72 4>;
};
};

2
sys/gnu/dts/arm/imx23-olinuxino.dts
View File

@ -23,7 +23,7 @@
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
bus-width = <4>;
broken-cd;
status = "okay";

10
sys/gnu/dts/arm/imx23.dtsi
View File

@ -267,6 +267,14 @@
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc0_sck_cfg: mmc0-sck-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
@ -422,7 +430,7 @@
clocks = <&clks 16>;
};
dcp@80028000 {
dcp: crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <53 54>;

8
sys/gnu/dts/arm/imx25-pinfunc.h
View File

@ -82,6 +82,7 @@
#define MX25_PAD_EB0__EB0 0x040 0x258 0x000 0x00 0x000
#define MX25_PAD_EB0__AUD4_TXD 0x040 0x258 0x464 0x04 0x000
#define MX25_PAD_EB0__GPIO_2_12 0x040 0x258 0x000 0x05 0x000
#define MX25_PAD_EB0__CSPI3_SS0 0x040 0x258 0x4bc 0x06 0x000
#define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000
#define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000
@ -102,11 +103,13 @@
#define MX25_PAD_CS4__NF_CE1 0x054 0x264 0x000 0x01 0x000
#define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x03 0x000
#define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x05 0x000
#define MX25_PAD_CS4__CSPI3_MOSI 0x054 0x264 0x4b8 0x06 0x000
#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000
#define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000
#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000
#define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000
#define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000
@ -114,6 +117,7 @@
#define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000
#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x03 0x000
#define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x05 0x000
#define MX25_PAD_ECB__CSPI3_SCLK 0x060 0x270 0x4ac 0x06 0x000
#define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000
#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000
@ -251,10 +255,12 @@
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x00 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
#define MX25_PAD_LD12__KPP_ROW6 0x0f8 0x2f0 0x544 0x04 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x05 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x00 0x000
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
#define MX25_PAD_LD13__KPP_ROW7 0x0fc 0x2f4 0x548 0x04 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x05 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x00 0x000
@ -512,9 +518,11 @@
#define MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x1d8 0x3d0 0x000 0x00 0x000
#define MX25_PAD_FEC_TX_EN__GPIO_3_9 0x1d8 0x3d0 0x000 0x05 0x000
#define MX25_PAD_FEC_TX_EN__KPP_ROW4 0x1d8 0x3d0 0x53c 0x06 0x000
#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x1dc 0x3d4 0x000 0x00 0x000
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x05 0x000
#define MX25_PAD_FEC_RDATA0__KPP_ROW5 0x1dc 0x3d4 0x540 0x06 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x00 0x000
/*

4
sys/gnu/dts/arm/imx25.dtsi
View File

@ -75,7 +75,7 @@
interrupt-parent = <&asic>;
ranges;
aips@43f00000 { /* AIPS1 */
bus@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -332,7 +332,7 @@
};
};
aips@53f00000 { /* AIPS2 */
bus@53f00000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
sys/gnu/dts/arm/imx27-phytec-phycard-s-rdk.dts
View File

@ -75,8 +75,8 @@
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
MX27_PAD_I2C_DATA__I2C_DATA 0x0
MX27_PAD_I2C_CLK__I2C_CLK 0x0
>;
};

2
sys/gnu/dts/arm/imx27.dtsi
View File

@ -525,7 +525,7 @@
reg = <0x10024600 0x200>;
};
sahara2: sahara@10025000 {
sahara2: crypto@10025000 {
compatible = "fsl,imx27-sahara";
reg = <0x10025000 0x1000>;
interrupts = <59>;

10
sys/gnu/dts/arm/imx28-apx4devkit.dts
View File

@ -183,10 +183,20 @@
pinctrl-0 = <&auart2_2pins_a>;
status = "okay";
};
usbphy1: usbphy@8007e000 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins_a>;
status = "okay";
};
};
};
ahb@80080000 {
usb1: usb@80090000 {
status = "okay";
};
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";

2
sys/gnu/dts/arm/imx28.dtsi
View File

@ -998,7 +998,7 @@
clocks = <&clks 26>;
};
dcp: dcp@80028000 {
dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53 54>;

4
sys/gnu/dts/arm/imx31.dtsi
View File

@ -63,7 +63,7 @@
ranges = <0 0x1fffc000 0x4000>;
};
aips@43f00000 { /* AIPS1 */
bus@43f00000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -225,7 +225,7 @@
};
};
aips@53f00000 { /* AIPS2 */
bus@53f00000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
sys/gnu/dts/arm/imx35.dtsi
View File

@ -66,7 +66,7 @@
cache-level = <2>;
};
aips1: aips@43f00000 {
aips1: bus@43f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -199,7 +199,7 @@
};
};
aips2: aips@53f00000 {
aips2: bus@53f00000 {
compatible = "fsl,aips", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
sys/gnu/dts/arm/imx50.dtsi
View File

@ -101,7 +101,7 @@
interrupt-parent = <&tzic>;
ranges;
aips@50000000 { /* AIPS1 */
bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -389,7 +389,7 @@
};
};
aips@60000000 { /* AIPS2 */
bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

5
sys/gnu/dts/arm/imx51-zii-rdu1.dts
View File

@ -217,8 +217,8 @@
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLEFT",
"Headphone Jack", "HPRIGHT";
"Headphone Jack", "TPA6130A2 HPLEFT",
"Headphone Jack", "TPA6130A2 HPRIGHT";
simple-audio-card,aux-devs = <&hpa1>;
sound_cpu: simple-audio-card,cpu {
@ -470,6 +470,7 @@
compatible = "ti,tpa6130a2";
reg = <0x60>;
Vdd-supply = <&reg_3p3v>;
sound-name-prefix = "TPA6130A2";
};
ds1341: rtc@68 {

17
sys/gnu/dts/arm/imx51.dtsi
View File

@ -104,6 +104,11 @@
#phy-cells = <0>;
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu_csi0>, <&ipu_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
@ -143,6 +148,14 @@
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
ipu_csi0: port@0 {
reg = <0>;
};
ipu_csi1: port@1 {
reg = <1>;
};
ipu_di0: port@2 {
reg = <2>;
@ -158,7 +171,7 @@
};
};
aips@70000000 { /* AIPS1 */
bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -440,7 +453,7 @@
};
};
aips@80000000 { /* AIPS2 */
bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
sys/gnu/dts/arm/imx53.dtsi
View File

@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
aips@50000000 { /* AIPS1 */
bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -654,7 +654,7 @@
};
};
aips@60000000 { /* AIPS2 */
bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

40
sys/gnu/dts/arm/imx6dl-colibri-eval-v3.dts
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2016 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

17
sys/gnu/dts/arm/imx6dl-pico-dwarf.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard";
compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
};

17
sys/gnu/dts/arm/imx6dl-pico-hobbit.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-pico-hobbit.dtsi"
/ {
model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard";
compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
};

17
sys/gnu/dts/arm/imx6dl-pico-nymph.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard";
compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
};

17
sys/gnu/dts/arm/imx6dl-pico-pi.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard";
compatible = "technexion,imx6dl-pico", "fsl,imx6dl";
};

16
sys/gnu/dts/arm/imx6dl-riotboard.dts
View File

@ -89,11 +89,25 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
phy-handle = <&rgmii_phy>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8035 PHY */
rgmii_phy: ethernet-phy@4 {
reg = <4>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
};
};
};
&gpio1 {

2
sys/gnu/dts/arm/imx6dl-yapp4-common.dtsi
View File

@ -562,6 +562,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
over-current-active-low;
status = "disabled";
};
@ -569,6 +570,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
vbus-supply = <&reg_usb_otg_vbus>;
over-current-active-low;
srp-disable;
hnp-disable;
adp-disable;

2
sys/gnu/dts/arm/imx6dl-yapp4-ursa.dts
View File

@ -38,7 +38,7 @@
};
&switch_ports {
/delete-node/ port@2;
/delete-node/ port@3;
};
&touchscreen {

8
sys/gnu/dts/arm/imx6dl.dtsi
View File

@ -44,6 +44,8 @@
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
cpu@1 {
@ -85,8 +87,8 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@2000000 {
iomuxc: iomuxc@20e0000 {
aips1: bus@2000000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
@ -101,7 +103,7 @@
};
};
aips2: aips-bus@2100000 {
aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;

40
sys/gnu/dts/arm/imx6q-apalis-eval.dts
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2017 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

40
sys/gnu/dts/arm/imx6q-apalis-ixora-v1.1.dts
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2017 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

40
sys/gnu/dts/arm/imx6q-apalis-ixora.dts
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2017 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;

7
sys/gnu/dts/arm/imx6q-b450v3.dts
View File

@ -65,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";

7
sys/gnu/dts/arm/imx6q-b650v3.dts
View File

@ -65,13 +65,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};
&ldb {
status = "okay";

11
sys/gnu/dts/arm/imx6q-b850v3.dts
View File

@ -53,17 +53,6 @@
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
<&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};
&ldb {
fsl,dual-channel;
status = "okay";

15
sys/gnu/dts/arm/imx6q-bx50v3.dtsi
View File

@ -377,3 +377,18 @@
#interrupt-cells = <1>;
};
};
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
<&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
<&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
};

16
sys/gnu/dts/arm/imx6q-marsboard.dts
View File

@ -111,8 +111,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
phy-handle = <&rgmii_phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8035 PHY */
rgmii_phy: ethernet-phy@4 {
reg = <4>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
};
};
};
&hdmi {

2
sys/gnu/dts/arm/imx6q-novena.dts
View File

@ -107,7 +107,7 @@
};
panel: panel {
compatible = "innolux,n133hse-ea1", "simple-panel";
compatible = "innolux,n133hse-ea1";
backlight = <&backlight>;
};

17
sys/gnu/dts/arm/imx6q-pico-dwarf.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard";
compatible = "technexion,imx6q-pico", "fsl,imx6q";
};

17
sys/gnu/dts/arm/imx6q-pico-hobbit.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-pico-hobbit.dtsi"
/ {
model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard";
compatible = "technexion,imx6q-pico", "fsl,imx6q";
};

17
sys/gnu/dts/arm/imx6q-pico-nymph.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard";
compatible = "technexion,imx6q-pico", "fsl,imx6q";
};

17
sys/gnu/dts/arm/imx6q-pico-pi.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2018 Technexion Ltd.
//
// Author: Wig Cheng <wig.cheng@technexion.com>
// Richard Hu <richard.hu@technexion.com>
// Tapani Utriainen <tapani@technexion.com>
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-pico-pi.dtsi"
/ {
model = "TechNexion PICO-IMX6 Quad Board and PI baseboard";
compatible = "technexion,imx6q-pico", "fsl,imx6q";
};

6
sys/gnu/dts/arm/imx6q.dtsi
View File

@ -49,6 +49,8 @@
arm-supply = <&reg_arm>;
pu-supply = <&reg_pu>;
soc-supply = <&reg_soc>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
};
cpu1: cpu@1 {
@ -164,7 +166,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@2000000 { /* AIPS1 */
bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;
@ -181,7 +183,7 @@
};
};
iomuxc: iomuxc@20e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6q-iomuxc";
};
};

42
sys/gnu/dts/arm/imx6qdl-apalis.dtsi
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2017 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
@ -180,7 +144,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-handle = <&ethphy>;
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;

40
sys/gnu/dts/arm/imx6qdl-colibri.dtsi
View File

@ -1,44 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2014-2016 Toradex AG
* Copyright 2014-2020 Toradex
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>

5
sys/gnu/dts/arm/imx6qdl-gw52xx.dtsi
View File

@ -313,6 +313,11 @@
interrupts = <12 2>;
wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
accel@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
};
};
&ldb {

5
sys/gnu/dts/arm/imx6qdl-gw53xx.dtsi
View File

@ -304,6 +304,11 @@
interrupts = <11 2>;
wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
accel@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
};
};
&ldb {

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