MFC r207639, r207643, r207687, r207688
r207639: Add IFCAP_LINKSTATE to cxgb r207643: T3 hardware filters + cxgbtool interface to this functionality. r207687: if_cxgb should not depend on the T3 firmware module directly. r207688: various doorbell adjustments
This commit is contained in:
Navdeep Parhar
parent
f5fa4d2e65
commit
63ae3fec8b
@ -204,6 +204,7 @@ struct sge_fl {
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uint32_t cidx;
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uint32_t pidx;
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uint32_t gen;
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uint32_t db_pending;
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bus_addr_t phys_addr;
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uint32_t cntxt_id;
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uint32_t empty;
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@ -232,6 +233,7 @@ struct sge_txq {
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uint32_t pidx;
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uint32_t gen;
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uint32_t unacked;
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uint32_t db_pending;
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struct tx_desc *desc;
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struct tx_sw_desc *sdesc;
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uint32_t token;
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@ -59,6 +59,9 @@ enum {
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CH_CLEAR_STATS,
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CH_GET_UP_LA,
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CH_GET_UP_IOQS,
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CH_SET_FILTER,
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CH_DEL_FILTER,
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CH_GET_FILTER,
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};
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/* statistics categories */
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@ -215,6 +218,29 @@ struct ch_up_ioqs {
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struct t3_ioq_entry *data;
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};
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struct ch_filter_tuple {
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uint32_t sip;
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uint32_t dip;
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uint16_t sport;
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uint16_t dport;
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uint16_t vlan:12;
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uint16_t vlan_prio:3;
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};
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struct ch_filter {
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uint32_t filter_id;
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struct ch_filter_tuple val;
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struct ch_filter_tuple mask;
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uint16_t mac_addr_idx;
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uint8_t mac_hit:1;
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uint8_t proto:2;
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uint8_t want_filter_id:1;
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uint8_t pass:1;
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uint8_t rss:1;
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uint8_t qset;
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};
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#define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg)
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#define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg)
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#define CHELSIO_GETMTUTAB _IOR('f', CH_GETMTUTAB, struct ch_mtus)
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@ -239,4 +265,7 @@ struct ch_up_ioqs {
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#define CHELSIO_GET_EEPROM _IOWR('f', CH_GET_EEPROM, struct ch_eeprom)
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#define CHELSIO_GET_UP_LA _IOWR('f', CH_GET_UP_LA, struct ch_up_la)
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#define CHELSIO_GET_UP_IOQS _IOWR('f', CH_GET_UP_IOQS, struct ch_up_ioqs)
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#define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter)
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#define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter)
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#define CHELSIO_GET_FILTER _IOWR('f', CH_GET_FILTER, struct ch_filter)
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#endif
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@ -99,6 +99,13 @@ static void cxgb_ext_intr_handler(void *, int);
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static void cxgb_tick_handler(void *, int);
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static void cxgb_tick(void *);
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static void setup_rss(adapter_t *sc);
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static int alloc_filters(struct adapter *);
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static int setup_hw_filters(struct adapter *);
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static int set_filter(struct adapter *, int, const struct filter_info *);
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static inline void mk_set_tcb_field(struct cpl_set_tcb_field *, unsigned int,
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unsigned int, u64, u64);
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static inline void set_tcb_field_ulp(struct cpl_set_tcb_field *, unsigned int,
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unsigned int, u64, u64);
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/* Attachment glue for the PCI controller end of the device. Each port of
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* the device is attached separately, as defined later.
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@ -981,7 +988,7 @@ cxgb_makedev(struct port_info *pi)
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#define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
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IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
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IFCAP_VLAN_HWTSO)
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IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE)
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#define CXGB_CAP_ENABLE (CXGB_CAP & ~IFCAP_TSO6)
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static int
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@ -1665,6 +1672,13 @@ cxgb_up(struct adapter *sc)
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if ((err = update_tpsram(sc)))
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goto out;
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if (is_offload(sc)) {
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sc->params.mc5.nservers = 0;
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sc->params.mc5.nroutes = 0;
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sc->params.mc5.nfilters = t3_mc5_size(&sc->mc5) -
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MC5_MIN_TIDS;
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}
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err = t3_init_hw(sc, 0);
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if (err)
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goto out;
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@ -1676,6 +1690,7 @@ cxgb_up(struct adapter *sc)
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if (err)
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goto out;
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alloc_filters(sc);
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setup_rss(sc);
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t3_intr_clear(sc);
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@ -1702,6 +1717,7 @@ cxgb_up(struct adapter *sc)
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if (!(sc->flags & QUEUES_BOUND)) {
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bind_qsets(sc);
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setup_hw_filters(sc);
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sc->flags |= QUEUES_BOUND;
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}
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@ -3080,6 +3096,139 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
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free(buf, M_DEVBUF);
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break;
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}
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case CHELSIO_SET_FILTER: {
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struct ch_filter *f = (struct ch_filter *)data;;
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struct filter_info *p;
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unsigned int nfilters = sc->params.mc5.nfilters;
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if (!is_offload(sc))
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return (EOPNOTSUPP); /* No TCAM */
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if (!(sc->flags & FULL_INIT_DONE))
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return (EAGAIN); /* mc5 not setup yet */
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if (nfilters == 0)
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return (EBUSY); /* TOE will use TCAM */
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/* sanity checks */
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if (f->filter_id >= nfilters ||
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(f->val.dip && f->mask.dip != 0xffffffff) ||
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(f->val.sport && f->mask.sport != 0xffff) ||
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(f->val.dport && f->mask.dport != 0xffff) ||
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(f->val.vlan && f->mask.vlan != 0xfff) ||
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(f->val.vlan_prio &&
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f->mask.vlan_prio != FILTER_NO_VLAN_PRI) ||
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(f->mac_addr_idx != 0xffff && f->mac_addr_idx > 15) ||
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f->qset >= SGE_QSETS ||
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sc->rrss_map[f->qset] >= RSS_TABLE_SIZE)
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return (EINVAL);
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/* Was allocated with M_WAITOK */
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KASSERT(sc->filters, ("filter table NULL\n"));
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p = &sc->filters[f->filter_id];
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if (p->locked)
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return (EPERM);
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bzero(p, sizeof(*p));
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p->sip = f->val.sip;
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p->sip_mask = f->mask.sip;
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p->dip = f->val.dip;
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p->sport = f->val.sport;
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p->dport = f->val.dport;
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p->vlan = f->mask.vlan ? f->val.vlan : 0xfff;
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p->vlan_prio = f->mask.vlan_prio ? (f->val.vlan_prio & 6) :
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FILTER_NO_VLAN_PRI;
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p->mac_hit = f->mac_hit;
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p->mac_vld = f->mac_addr_idx != 0xffff;
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p->mac_idx = f->mac_addr_idx;
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p->pkt_type = f->proto;
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p->report_filter_id = f->want_filter_id;
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p->pass = f->pass;
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p->rss = f->rss;
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p->qset = f->qset;
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error = set_filter(sc, f->filter_id, p);
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if (error == 0)
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p->valid = 1;
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break;
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}
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case CHELSIO_DEL_FILTER: {
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struct ch_filter *f = (struct ch_filter *)data;
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struct filter_info *p;
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unsigned int nfilters = sc->params.mc5.nfilters;
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if (!is_offload(sc))
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return (EOPNOTSUPP);
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if (!(sc->flags & FULL_INIT_DONE))
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return (EAGAIN);
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if (nfilters == 0 || sc->filters == NULL)
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return (EINVAL);
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if (f->filter_id >= nfilters)
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return (EINVAL);
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p = &sc->filters[f->filter_id];
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if (p->locked)
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return (EPERM);
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if (!p->valid)
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return (EFAULT); /* Read "Bad address" as "Bad index" */
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bzero(p, sizeof(*p));
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p->sip = p->sip_mask = 0xffffffff;
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p->vlan = 0xfff;
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p->vlan_prio = FILTER_NO_VLAN_PRI;
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p->pkt_type = 1;
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error = set_filter(sc, f->filter_id, p);
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break;
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}
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case CHELSIO_GET_FILTER: {
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struct ch_filter *f = (struct ch_filter *)data;
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struct filter_info *p;
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unsigned int i, nfilters = sc->params.mc5.nfilters;
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if (!is_offload(sc))
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return (EOPNOTSUPP);
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if (!(sc->flags & FULL_INIT_DONE))
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return (EAGAIN);
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if (nfilters == 0 || sc->filters == NULL)
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return (EINVAL);
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i = f->filter_id == 0xffffffff ? 0 : f->filter_id + 1;
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for (; i < nfilters; i++) {
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p = &sc->filters[i];
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if (!p->valid)
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continue;
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bzero(f, sizeof(*f));
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f->filter_id = i;
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f->val.sip = p->sip;
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f->mask.sip = p->sip_mask;
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f->val.dip = p->dip;
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f->mask.dip = p->dip ? 0xffffffff : 0;
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f->val.sport = p->sport;
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f->mask.sport = p->sport ? 0xffff : 0;
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f->val.dport = p->dport;
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f->mask.dport = p->dport ? 0xffff : 0;
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f->val.vlan = p->vlan == 0xfff ? 0 : p->vlan;
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f->mask.vlan = p->vlan == 0xfff ? 0 : 0xfff;
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f->val.vlan_prio = p->vlan_prio == FILTER_NO_VLAN_PRI ?
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0 : p->vlan_prio;
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f->mask.vlan_prio = p->vlan_prio == FILTER_NO_VLAN_PRI ?
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0 : FILTER_NO_VLAN_PRI;
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f->mac_hit = p->mac_hit;
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f->mac_addr_idx = p->mac_vld ? p->mac_idx : 0xffff;
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f->proto = p->pkt_type;
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f->want_filter_id = p->report_filter_id;
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f->pass = p->pass;
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f->rss = p->rss;
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f->qset = p->qset;
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break;
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}
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if (i == nfilters)
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f->filter_id = 0xffffffff;
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break;
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}
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default:
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return (EOPNOTSUPP);
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break;
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@ -3134,5 +3283,127 @@ cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf)
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XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
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}
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static int
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alloc_filters(struct adapter *sc)
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{
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struct filter_info *p;
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unsigned int nfilters = sc->params.mc5.nfilters;
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MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1);
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if (nfilters == 0)
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return (0);
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p = malloc(sizeof(*p) * nfilters, M_DEVBUF, M_WAITOK | M_ZERO);
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sc->filters = p;
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p = &sc->filters[nfilters - 1];
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p->vlan = 0xfff;
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p->vlan_prio = FILTER_NO_VLAN_PRI;
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p->pass = p->rss = p->valid = p->locked = 1;
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return (0);
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}
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static int
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setup_hw_filters(struct adapter *sc)
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{
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int i, rc;
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unsigned int nfilters = sc->params.mc5.nfilters;
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if (!sc->filters)
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return (0);
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t3_enable_filters(sc);
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for (i = rc = 0; i < nfilters && !rc; i++) {
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if (sc->filters[i].locked)
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rc = set_filter(sc, i, &sc->filters[i]);
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}
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return (rc);
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}
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static int
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set_filter(struct adapter *sc, int id, const struct filter_info *f)
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{
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int len;
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struct mbuf *m;
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struct ulp_txpkt *txpkt;
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struct work_request_hdr *wr;
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struct cpl_pass_open_req *oreq;
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struct cpl_set_tcb_field *sreq;
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len = sizeof(*wr) + sizeof(*oreq) + 2 * sizeof(*sreq);
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KASSERT(len <= MHLEN, ("filter request too big for an mbuf"));
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id += t3_mc5_size(&sc->mc5) - sc->params.mc5.nroutes -
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sc->params.mc5.nfilters;
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m = m_gethdr(M_WAITOK, MT_DATA);
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m->m_len = m->m_pkthdr.len = len;
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bzero(mtod(m, char *), len);
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wr = mtod(m, struct work_request_hdr *);
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wr->wrh_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS) | F_WR_ATOMIC);
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oreq = (struct cpl_pass_open_req *)(wr + 1);
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txpkt = (struct ulp_txpkt *)oreq;
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txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT));
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txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*oreq) / 8));
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OPCODE_TID(oreq) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, id));
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oreq->local_port = htons(f->dport);
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oreq->peer_port = htons(f->sport);
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oreq->local_ip = htonl(f->dip);
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oreq->peer_ip = htonl(f->sip);
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oreq->peer_netmask = htonl(f->sip_mask);
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oreq->opt0h = 0;
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oreq->opt0l = htonl(F_NO_OFFLOAD);
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oreq->opt1 = htonl(V_MAC_MATCH_VALID(f->mac_vld) |
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V_CONN_POLICY(CPL_CONN_POLICY_FILTER) |
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V_VLAN_PRI(f->vlan_prio >> 1) |
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V_VLAN_PRI_VALID(f->vlan_prio != FILTER_NO_VLAN_PRI) |
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V_PKT_TYPE(f->pkt_type) | V_OPT1_VLAN(f->vlan) |
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V_MAC_MATCH(f->mac_idx | (f->mac_hit << 4)));
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sreq = (struct cpl_set_tcb_field *)(oreq + 1);
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set_tcb_field_ulp(sreq, id, 1, 0x1800808000ULL,
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(f->report_filter_id << 15) | (1 << 23) |
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((u64)f->pass << 35) | ((u64)!f->rss << 36));
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set_tcb_field_ulp(sreq + 1, id, 0, 0xffffffff, (2 << 19) | 1);
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t3_mgmt_tx(sc, m);
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if (f->pass && !f->rss) {
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len = sizeof(*sreq);
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m = m_gethdr(M_WAITOK, MT_DATA);
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m->m_len = m->m_pkthdr.len = len;
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bzero(mtod(m, char *), len);
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sreq = mtod(m, struct cpl_set_tcb_field *);
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sreq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
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mk_set_tcb_field(sreq, id, 25, 0x3f80000,
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(u64)sc->rrss_map[f->qset] << 19);
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t3_mgmt_tx(sc, m);
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}
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return 0;
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}
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static inline void
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mk_set_tcb_field(struct cpl_set_tcb_field *req, unsigned int tid,
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unsigned int word, u64 mask, u64 val)
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{
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OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
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req->reply = V_NO_REPLY(1);
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req->cpu_idx = 0;
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req->word = htons(word);
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req->mask = htobe64(mask);
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req->val = htobe64(val);
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}
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static inline void
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set_tcb_field_ulp(struct cpl_set_tcb_field *req, unsigned int tid,
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unsigned int word, u64 mask, u64 val)
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{
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struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
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txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT));
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txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*req) / 8));
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mk_set_tcb_field(req, tid, word, mask, val);
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}
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@ -696,7 +696,7 @@ refill_fl(adapter_t *sc, struct sge_fl *q, int n)
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struct refill_fl_cb_arg cb_arg;
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struct mbuf *m;
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caddr_t cl;
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int err, count = 0;
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int err;
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cb_arg.error = 0;
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while (n--) {
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@ -754,12 +754,14 @@ refill_fl(adapter_t *sc, struct sge_fl *q, int n)
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d = q->desc;
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}
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q->credits++;
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count++;
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q->db_pending++;
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}
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done:
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if (count)
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if (q->db_pending >= 32) {
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q->db_pending = 0;
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t3_write_reg(sc, A_SG_KDOORBELL, V_EGRCNTX(q->cntxt_id));
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}
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}
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@ -810,8 +812,10 @@ __refill_fl(adapter_t *adap, struct sge_fl *fl)
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static __inline void
|
||||
__refill_fl_lt(adapter_t *adap, struct sge_fl *fl, int max)
|
||||
{
|
||||
if ((fl->size - fl->credits) < max)
|
||||
refill_fl(adap, fl, min(max, fl->size - fl->credits));
|
||||
uint32_t reclaimable = fl->size - fl->credits;
|
||||
|
||||
if (reclaimable > 0)
|
||||
refill_fl(adap, fl, min(max, reclaimable));
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1261,7 +1265,7 @@ make_sgl(struct sg_ent *sgp, bus_dma_segment_t *segs, int nsegs)
|
||||
* When GTS is disabled we unconditionally ring the doorbell.
|
||||
*/
|
||||
static __inline void
|
||||
check_ring_tx_db(adapter_t *adap, struct sge_txq *q)
|
||||
check_ring_tx_db(adapter_t *adap, struct sge_txq *q, int mustring)
|
||||
{
|
||||
#if USE_GTS
|
||||
clear_bit(TXQ_LAST_PKT_DB, &q->flags);
|
||||
@ -1275,9 +1279,12 @@ check_ring_tx_db(adapter_t *adap, struct sge_txq *q)
|
||||
F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
|
||||
}
|
||||
#else
|
||||
wmb(); /* write descriptors before telling HW */
|
||||
t3_write_reg(adap, A_SG_KDOORBELL,
|
||||
F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
|
||||
if (mustring || ++q->db_pending >= 32) {
|
||||
wmb(); /* write descriptors before telling HW */
|
||||
t3_write_reg(adap, A_SG_KDOORBELL,
|
||||
F_SELEGRCNTX | V_EGRCNTX(q->cntxt_id));
|
||||
q->db_pending = 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -1480,7 +1487,7 @@ t3_encap(struct sge_qset *qs, struct mbuf **m)
|
||||
wmb();
|
||||
ETHER_BPF_MTAP(pi->ifp, m0);
|
||||
wr_gen2(txd, txqs.gen);
|
||||
check_ring_tx_db(sc, txq);
|
||||
check_ring_tx_db(sc, txq, 0);
|
||||
return (0);
|
||||
} else if (tso_info) {
|
||||
int eth_type;
|
||||
@ -1543,7 +1550,7 @@ t3_encap(struct sge_qset *qs, struct mbuf **m)
|
||||
wmb();
|
||||
ETHER_BPF_MTAP(pi->ifp, m0);
|
||||
wr_gen2(txd, txqs.gen);
|
||||
check_ring_tx_db(sc, txq);
|
||||
check_ring_tx_db(sc, txq, 0);
|
||||
m_freem(m0);
|
||||
return (0);
|
||||
}
|
||||
@ -1574,7 +1581,7 @@ t3_encap(struct sge_qset *qs, struct mbuf **m)
|
||||
wmb();
|
||||
ETHER_BPF_MTAP(pi->ifp, m0);
|
||||
wr_gen2(txd, txqs.gen);
|
||||
check_ring_tx_db(sc, txq);
|
||||
check_ring_tx_db(sc, txq, 0);
|
||||
m_freem(m0);
|
||||
return (0);
|
||||
}
|
||||
@ -1593,7 +1600,7 @@ t3_encap(struct sge_qset *qs, struct mbuf **m)
|
||||
wr_lo = htonl(V_WR_TID(txq->token));
|
||||
write_wr_hdr_sgl(ndesc, txd, &txqs, txq, sgl, flits,
|
||||
sgl_flits, wr_hi, wr_lo);
|
||||
check_ring_tx_db(sc, txq);
|
||||
check_ring_tx_db(sc, txq, 0);
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -1643,7 +1650,6 @@ cxgb_start_locked(struct sge_qset *qs)
|
||||
{
|
||||
struct mbuf *m_head = NULL;
|
||||
struct sge_txq *txq = &qs->txq[TXQ_ETH];
|
||||
int in_use_init = txq->in_use;
|
||||
struct port_info *pi = qs->port;
|
||||
struct ifnet *ifp = pi->ifp;
|
||||
|
||||
@ -1655,8 +1661,7 @@ cxgb_start_locked(struct sge_qset *qs)
|
||||
return;
|
||||
}
|
||||
TXQ_LOCK_ASSERT(qs);
|
||||
while ((txq->in_use - in_use_init < TX_START_MAX_DESC) &&
|
||||
!TXQ_RING_EMPTY(qs) && (ifp->if_drv_flags & IFF_DRV_RUNNING) &&
|
||||
while (!TXQ_RING_EMPTY(qs) && (ifp->if_drv_flags & IFF_DRV_RUNNING) &&
|
||||
pi->link_config.link_ok) {
|
||||
reclaim_completed_tx(qs, cxgb_tx_reclaim_threshold, TXQ_ETH);
|
||||
|
||||
@ -1674,6 +1679,10 @@ cxgb_start_locked(struct sge_qset *qs)
|
||||
|
||||
m_head = NULL;
|
||||
}
|
||||
|
||||
if (txq->db_pending)
|
||||
check_ring_tx_db(pi->adapter, txq, 1);
|
||||
|
||||
if (!TXQ_RING_EMPTY(qs) && callout_pending(&txq->txq_timer) == 0 &&
|
||||
pi->link_config.link_ok)
|
||||
callout_reset_on(&txq->txq_timer, 1, cxgb_tx_timeout,
|
||||
@ -1707,6 +1716,9 @@ cxgb_transmit_locked(struct ifnet *ifp, struct sge_qset *qs, struct mbuf *m)
|
||||
(error = drbr_enqueue(ifp, br, m)) != 0)
|
||||
return (error);
|
||||
} else {
|
||||
if (txq->db_pending)
|
||||
check_ring_tx_db(pi->adapter, txq, 1);
|
||||
|
||||
/*
|
||||
* We've bypassed the buf ring so we need to update
|
||||
* the stats directly
|
||||
@ -2354,7 +2366,7 @@ again: reclaim_completed_tx(qs, 16, TXQ_OFLD);
|
||||
TXQ_UNLOCK(qs);
|
||||
|
||||
write_ofld_wr(adap, m, q, pidx, gen, ndesc, segs, nsegs);
|
||||
check_ring_tx_db(adap, q);
|
||||
check_ring_tx_db(adap, q, 1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -3033,7 +3045,7 @@ process_responses(adapter_t *adap, struct sge_qset *qs, int budget)
|
||||
r = rspq->desc;
|
||||
}
|
||||
|
||||
if (++rspq->credits >= (rspq->size / 4)) {
|
||||
if (++rspq->credits >= 64) {
|
||||
refill_rspq(adap, rspq, rspq->credits);
|
||||
rspq->credits = 0;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user