Vendor import of llvm release_39 branch r288847:
https://llvm.org/svn/llvm-project/llvm/branches/release_39@288847
This commit is contained in:
Dimitry Andric
parent
2cf3bd4601
commit
6421cca32f
@ -718,13 +718,21 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
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.addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
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.addOperand(DesiredLo)
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.addImm(0);
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::SBCSXr), AArch64::XZR)
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
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.addReg(AArch64::WZR)
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.addReg(AArch64::WZR)
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.addImm(AArch64CC::EQ);
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
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.addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
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.addOperand(DesiredHi);
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
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.addImm(AArch64CC::NE)
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.addMBB(DoneBB)
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.addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
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.addOperand(DesiredHi)
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.addImm(0);
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
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.addReg(StatusReg, RegState::Kill)
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.addReg(StatusReg, RegState::Kill)
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.addImm(AArch64CC::EQ);
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BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
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.addReg(StatusReg, RegState::Kill)
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.addMBB(DoneBB);
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LoadCmpBB->addSuccessor(DoneBB);
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LoadCmpBB->addSuccessor(StoreBB);
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@ -10083,17 +10083,24 @@ static void ReplaceReductionResults(SDNode *N,
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Results.push_back(SplitVal);
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}
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static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
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SDLoc DL(N);
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SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N);
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SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64,
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DAG.getNode(ISD::SRL, DL, MVT::i128, N,
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DAG.getConstant(64, DL, MVT::i64)));
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return std::make_pair(Lo, Hi);
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}
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static void ReplaceCMP_SWAP_128Results(SDNode *N,
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SmallVectorImpl<SDValue> & Results,
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SelectionDAG &DAG) {
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assert(N->getValueType(0) == MVT::i128 &&
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"AtomicCmpSwap on types less than 128 should be legal");
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SDValue Ops[] = {N->getOperand(1),
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N->getOperand(2)->getOperand(0),
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N->getOperand(2)->getOperand(1),
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N->getOperand(3)->getOperand(0),
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N->getOperand(3)->getOperand(1),
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N->getOperand(0)};
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auto Desired = splitInt128(N->getOperand(2), DAG);
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auto New = splitInt128(N->getOperand(3), DAG);
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SDValue Ops[] = {N->getOperand(1), Desired.first, Desired.second,
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New.first, New.second, N->getOperand(0)};
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SDNode *CmpSwap = DAG.getMachineNode(
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AArch64::CMP_SWAP_128, SDLoc(N),
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DAG.getVTList(MVT::i64, MVT::i64, MVT::i32, MVT::Other), Ops);
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@ -932,13 +932,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
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.addReg(DestLo, getKillRegState(Dest.isDead()))
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.addReg(DesiredLo, getKillRegState(Desired.isDead())));
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unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr;
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MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr))
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.addReg(StatusReg, RegState::Define | RegState::Dead)
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.addReg(DestHi, getKillRegState(Dest.isDead()))
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.addReg(DesiredHi, getKillRegState(Desired.isDead()));
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AddDefaultPred(MIB);
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MIB.addReg(ARM::CPSR, RegState::Kill);
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BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
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.addReg(DestHi, getKillRegState(Dest.isDead()))
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.addReg(DesiredHi, getKillRegState(Desired.isDead()))
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.addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
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unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
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BuildMI(LoadCmpBB, DL, TII->get(Bcc))
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@ -65,11 +65,41 @@ define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nou
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [x0]
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; CHECK: cmp [[OLD_LO]], x2
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; CHECK: sbcs xzr, [[OLD_HI]], x3
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; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
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; CHECK: cmp [[OLD_HI]], x3
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; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
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; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, [x0]
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; CHECK: cbnz [[STATUS]], [[RETRY]]
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; CHECK: [[DONE]]:
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%res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic
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ret { i128, i1 } %res
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}
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; Original implementation assumed the desired & new arguments had already been
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; type-legalized into some kind of BUILD_PAIR operation and crashed when this
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; was false.
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@var128 = global i128 0
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define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) {
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; CHECK-LABEL: test_cmpxchg_128_unsplit:
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; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
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; CHECK: ldr [[DESIRED_HI:x[0-9]+]], [x[[VAR128]], #8]
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; CHECK: ldr [[DESIRED_LO:x[0-9]+]], [x[[VAR128]]]
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; CHECK: ldr [[NEW_HI:x[0-9]+]], [x[[VAR128]], #8]
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; CHECK: ldr [[NEW_LO:x[0-9]+]], [x[[VAR128]]]
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [x0]
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; CHECK: cmp [[OLD_LO]], [[DESIRED_LO]]
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; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
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; CHECK: cmp [[OLD_HI]], [[DESIRED_HI]]
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; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
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; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], [x0]
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; CHECK: cbnz [[STATUS]], [[RETRY]]
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; CHECK: [[DONE]]:
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%desired = load volatile i128, i128* @var128
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%new = load volatile i128, i128* @var128
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%val = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
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ret { i128, i1 } %val
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}
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@ -69,9 +69,9 @@ define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
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; CHECK: cmp [[OLDLO]], r6
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; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], r7
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; CHECK: cmpeq [[OLDHI]], r7
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; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: strexd [[STATUS]], r4, r5, [r0]
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; CHECK: strexd [[STATUS:r[0-9]+]], r4, r5, [r0]
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; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
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; CHECK: bne [[RETRY]]
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; CHECK: [[DONE]]:
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@ -87,9 +87,9 @@ define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
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; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
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; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
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; CHECK: cmp [[OLDLO]], {{r[0-9]+}}
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; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], {{r[0-9]+}}
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; CHECK: cmpeq [[OLDHI]], {{r[0-9]+}}
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; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
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; CHECK: strexd [[STATUS]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
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; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
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; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
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; CHECK: bne [[RETRY]]
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; CHECK: [[DONE]]:
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