Support soft power-off via the ACPI S5 state for bhyve guests.
- Implement the PM1_EVT and PM1_CTL registers required by ACPI.
The PM1_EVT register is mostly a dummy as bhyve doesn't support any
of the hardware-initiated events. The only bit of PM1_CNT that is
implemented are the sleep request bits (SPL_EN and SLP_TYP) which
request a graceful power off for S5. In particular, for S5, bhyve
exits with a non-zero value which terminates the loop in vmrun.sh.
- Emulate the Reset Control register at I/O port 0xcf9 and advertise
it as the reset register via ACPI.
- Advertise an _S5 package.
- Extend the in/out interface to allow an in/out handler to request
that the hypervisor trigger a reset or power-off.
- While here, note that all vCPUs in a guest support C1 ("hlt").
Reviewed by: neel (earlier version)
This commit is contained in:
John Baldwin
parent
3c6aaa556d
commit
6450da0774
@ -10,7 +10,7 @@ MAN= bhyve.8
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SRCS= acpi.c atpic.c bhyverun.c block_if.c consport.c dbgport.c elcr.c
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SRCS+= inout.c legacy_irq.c mem.c mevent.c mptbl.c pci_ahci.c
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SRCS+= pci_emul.c pci_hostbridge.c pci_lpc.c pci_passthru.c pci_virtio_block.c
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SRCS+= pci_virtio_net.c pci_uart.c pit_8254.c pmtmr.c post.c rtc.c
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SRCS+= pci_virtio_net.c pci_uart.c pit_8254.c pm.c pmtmr.c post.c rtc.c
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SRCS+= uart_emul.c virtio.c xmsr.c spinup_ap.c
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.PATH: ${.CURDIR}/../../sys/amd64/vmm
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@ -85,6 +85,8 @@ __FBSDID("$FreeBSD$");
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#define BHYVE_ASL_SUFFIX ".aml"
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#define BHYVE_ASL_COMPILER "/usr/sbin/iasl"
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#define BHYVE_PM1A_EVT_ADDR 0x400
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#define BHYVE_PM1A_CNT_ADDR 0x404
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#define BHYVE_PM_TIMER_ADDR 0x408
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static int basl_keep_temps;
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@ -342,9 +344,11 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tACPI Disable Value : 00\n");
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EFPRINTF(fp, "[0001]\t\tS4BIOS Command : 00\n");
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EFPRINTF(fp, "[0001]\t\tP-State Control : 00\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Event Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Event Block Address : %08X\n",
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BHYVE_PM1A_EVT_ADDR);
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EFPRINTF(fp, "[0004]\t\tPM1B Event Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Control Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM1A Control Block Address : %08X\n",
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BHYVE_PM1A_CNT_ADDR);
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EFPRINTF(fp, "[0004]\t\tPM1B Control Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM2 Control Block Address : 00000000\n");
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EFPRINTF(fp, "[0004]\t\tPM Timer Block Address : %08X\n",
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@ -379,7 +383,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0004]\t\tFlags (decoded below) : 00000000\n");
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EFPRINTF(fp, "\t\t\tWBINVD instruction is operational (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tWBINVD flushes all caches (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tAll CPUs support C1 (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tAll CPUs support C1 (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tC2 works on MP system (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tControl Method Power Button (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tControl Method Sleep Button (V1) : 1\n");
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@ -387,7 +391,7 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "\t\t\tRTC can wake system from S4 (V1) : 0\n");
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EFPRINTF(fp, "\t\t\t32-bit PM Timer (V1) : 1\n");
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EFPRINTF(fp, "\t\t\tDocking Supported (V1) : 0\n");
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EFPRINTF(fp, "\t\t\tReset Register Supported (V2) : 0\n");
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EFPRINTF(fp, "\t\t\tReset Register Supported (V2) : 1\n");
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EFPRINTF(fp, "\t\t\tSealed Case (V3) : 0\n");
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EFPRINTF(fp, "\t\t\tHeadless - No Video (V3) : 1\n");
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EFPRINTF(fp, "\t\t\tUse native instr after SLP_TYPx (V3) : 0\n");
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@ -407,10 +411,10 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tBit Width : 08\n");
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EFPRINTF(fp, "[0001]\t\tBit Offset : 00\n");
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EFPRINTF(fp, "[0001]\t\tEncoded Access Width : 01 [Byte Access:8]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 0000000000000001\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 0000000000000CF9\n");
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EFPRINTF(fp, "\n");
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EFPRINTF(fp, "[0001]\t\tValue to cause reset : 00\n");
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EFPRINTF(fp, "[0001]\t\tValue to cause reset : 06\n");
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EFPRINTF(fp, "[0003]\t\tReserved : 000000\n");
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EFPRINTF(fp, "[0008]\t\tFACS Address : 00000000%08X\n",
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basl_acpi_base + FACS_OFFSET);
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@ -422,7 +426,8 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tBit Width : 20\n");
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EFPRINTF(fp, "[0001]\t\tBit Offset : 00\n");
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EFPRINTF(fp, "[0001]\t\tEncoded Access Width : 02 [Word Access:16]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 0000000000000001\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
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BHYVE_PM1A_EVT_ADDR);
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EFPRINTF(fp, "\n");
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EFPRINTF(fp,
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@ -441,7 +446,8 @@ basl_fwrite_fadt(FILE *fp)
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EFPRINTF(fp, "[0001]\t\tBit Width : 10\n");
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EFPRINTF(fp, "[0001]\t\tBit Offset : 00\n");
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EFPRINTF(fp, "[0001]\t\tEncoded Access Width : 02 [Word Access:16]\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 0000000000000001\n");
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EFPRINTF(fp, "[0008]\t\tAddress : 00000000%08X\n",
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BHYVE_PM1A_CNT_ADDR);
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EFPRINTF(fp, "\n");
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EFPRINTF(fp,
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@ -613,6 +619,11 @@ basl_fwrite_dsdt(FILE *fp)
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EFPRINTF(fp, "DefinitionBlock (\"bhyve_dsdt.aml\", \"DSDT\", 2,"
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"\"BHYVE \", \"BVDSDT \", 0x00000001)\n");
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EFPRINTF(fp, "{\n");
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EFPRINTF(fp, " Name (_S5, Package (0x02)\n");
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EFPRINTF(fp, " {\n");
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EFPRINTF(fp, " 0x05,\n");
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EFPRINTF(fp, " Zero,\n");
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EFPRINTF(fp, " })\n");
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EFPRINTF(fp, " Scope (_SB)\n");
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EFPRINTF(fp, " {\n");
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EFPRINTF(fp, " Device (PCI0)\n");
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@ -72,6 +72,7 @@ __FBSDID("$FreeBSD$");
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#define VMEXIT_RESTART 2 /* restart current instruction */
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#define VMEXIT_ABORT 3 /* abort the vm run loop */
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#define VMEXIT_RESET 4 /* guest machine has reset */
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#define VMEXIT_POWEROFF 5 /* guest machine has powered off */
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#define MB (1024UL * 1024)
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#define GB (1024UL * MB)
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@ -296,12 +297,17 @@ vmexit_inout(struct vmctx *ctx, struct vm_exit *vme, int *pvcpu)
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return (vmexit_handle_notify(ctx, vme, pvcpu, eax));
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error = emulate_inout(ctx, vcpu, in, port, bytes, &eax, strictio);
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if (error == 0 && in)
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if (error == INOUT_OK && in)
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error = vm_set_register(ctx, vcpu, VM_REG_GUEST_RAX, eax);
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if (error == 0)
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switch (error) {
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case INOUT_OK:
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return (VMEXIT_CONTINUE);
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else {
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case INOUT_RESET:
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return (VMEXIT_RESET);
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case INOUT_POWEROFF:
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return (VMEXIT_POWEROFF);
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default:
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fprintf(stderr, "Unhandled %s%c 0x%04x\n",
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in ? "in" : "out",
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bytes == 1 ? 'b' : (bytes == 2 ? 'w' : 'l'), port);
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@ -33,6 +33,12 @@
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struct vmctx;
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/* Handler return values. */
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#define INOUT_ERROR -1
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#define INOUT_OK 0
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#define INOUT_RESET 1
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#define INOUT_POWEROFF 2
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typedef int (*inout_func_t)(struct vmctx *ctx, int vcpu, int in, int port,
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int bytes, uint32_t *eax, void *arg);
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139
usr.sbin/bhyve/pm.c
Normal file
139
usr.sbin/bhyve/pm.c
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@ -0,0 +1,139 @@
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/*-
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* Copyright (c) 2013 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include "inout.h"
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#define PM1A_EVT_ADDR 0x400
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#define PM1A_CNT_ADDR 0x404
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/*
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* Reset Control register at I/O port 0xcf9. Bit 2 forces a system
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* reset when it transitions from 0 to 1. Bit 1 selects the type of
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* reset to attempt: 0 selects a "soft" reset, and 1 selects a "hard"
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* reset.
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*/
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static int
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reset_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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static uint8_t reset_control;
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if (bytes != 1)
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return (-1);
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if (in)
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*eax = reset_control;
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else {
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reset_control = *eax;
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/* Treat hard and soft resets the same. */
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if (reset_control & 0x4)
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return (INOUT_RESET);
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}
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return (0);
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}
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INOUT_PORT(reset_reg, 0xCF9, IOPORT_F_INOUT, reset_handler);
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/*
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* Power Management 1 Event Registers
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*
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* bhyve doesn't support any power management events currently, so the
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* status register always returns zero. The enable register preserves
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* its value but has no effect.
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*/
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static int
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pm1_status_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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if (bytes != 2)
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return (-1);
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if (in)
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*eax = 0;
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return (0);
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}
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static int
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pm1_enable_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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static uint16_t pm1_enable;
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if (bytes != 2)
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return (-1);
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if (in)
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*eax = pm1_enable;
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else
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pm1_enable = *eax;
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return (0);
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}
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INOUT_PORT(pm1_status, PM1A_EVT_ADDR, IOPORT_F_INOUT, pm1_status_handler);
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INOUT_PORT(pm1_enable, PM1A_EVT_ADDR + 2, IOPORT_F_INOUT, pm1_enable_handler);
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/*
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* Power Management 1 Control Register
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*
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* This is mostly unimplemented except that we wish to handle writes that
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* set SPL_EN to handle S5 (soft power off).
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*/
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#define PM1_SLP_TYP 0x1c00
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#define PM1_SLP_EN 0x2000
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#define PM1_ALWAYS_ZERO 0xc003
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static int
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pm1_control_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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static uint16_t pm1_control;
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if (bytes != 2)
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return (-1);
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if (in)
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*eax = pm1_control;
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else {
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/*
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* Various bits are write-only or reserved, so force them
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* to zero in pm1_control.
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*/
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pm1_control = *eax & ~(PM1_SLP_EN | PM1_ALWAYS_ZERO);
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/*
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* If SLP_EN is set, check for S5. Bhyve's _S5_ method
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* says that '5' should be stored in SLP_TYP for S5.
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*/
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if (*eax & PM1_SLP_EN) {
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if ((pm1_control & PM1_SLP_TYP) >> 10 == 5)
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return (INOUT_POWEROFF);
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}
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}
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return (0);
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}
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INOUT_PORT(pm1_control, PM1A_CNT_ADDR, IOPORT_F_INOUT, pm1_control_handler);
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