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The minimim grant and maximum latency PCI config registers are only valid

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for type 0 devices, not type 1 or 2 bridges.  Don't read them for bridge
devices during bus scans and return an error when attempting to read them
as ivars for bridge devices.
This commit is contained in:
John Baldwin 2015-04-22 21:41:59 +00:00
parent f2d55827ea
commit 65c7c1b424
1 changed files with 10 additions and 3 deletions
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13
sys/dev/pci/pci.c
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@ -583,6 +583,8 @@ pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
case PCIM_HDRTYPE_NORMAL:
cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
cfg->mingnt = REG(PCIR_MINGNT, 1);
cfg->maxlat = REG(PCIR_MAXLAT, 1);
cfg->nummaps = PCI_MAXMAPS_0;
break;
case PCIM_HDRTYPE_BRIDGE:
@ -641,9 +643,6 @@ pci_fill_devinfo(device_t pcib, int d, int b, int s, int f, uint16_t vid,
cfg->intpin = REG(PCIR_INTPIN, 1);
cfg->intline = REG(PCIR_INTLINE, 1);
cfg->mingnt = REG(PCIR_MINGNT, 1);
cfg->maxlat = REG(PCIR_MAXLAT, 1);
cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
cfg->hdrtype &= ~PCIM_MFDEV;
STAILQ_INIT(&cfg->maps);
@ -4425,9 +4424,17 @@ pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
*result = cfg->cachelnsz;
break;
case PCI_IVAR_MINGNT:
if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
*result = -1;
return (EINVAL);
}
*result = cfg->mingnt;
break;
case PCI_IVAR_MAXLAT:
if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
*result = -1;
return (EINVAL);
}
*result = cfg->maxlat;
break;
case PCI_IVAR_LATTIMER: