Use "Ibex Peak" codename for "5 Series/3400 Series" chipsets.
This is shorter and unifies naming with later chipsets. MFC after: 1 week
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@ -111,12 +111,12 @@ static const struct {
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{0x3a058086, 0x00, "Intel ICH10 (RAID)", 0},
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{0x3a228086, 0x00, "Intel ICH10", 0},
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{0x3a258086, 0x00, "Intel ICH10 (RAID)", 0},
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{0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
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{0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
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{0x3b258086, 0x00, "Intel 5 Series/3400 Series (RAID)", 0},
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{0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
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{0x3b2c8086, 0x00, "Intel 5 Series/3400 Series (RAID)", 0},
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{0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
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{0x3b228086, 0x00, "Intel Ibex Peak", 0},
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{0x3b238086, 0x00, "Intel Ibex Peak", 0},
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{0x3b258086, 0x00, "Intel Ibex Peak (RAID)", 0},
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{0x3b298086, 0x00, "Intel Ibex Peak-M", 0},
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{0x3b2c8086, 0x00, "Intel Ibex Peak-M (RAID)", 0},
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{0x3b2f8086, 0x00, "Intel Ibex Peak-M Series", 0},
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{0x19b08086, 0x00, "Intel Denverton", 0},
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{0x19b18086, 0x00, "Intel Denverton", 0},
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{0x19b28086, 0x00, "Intel Denverton", 0},
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@ -193,12 +193,12 @@ struct ata_pci_controller {
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#define ATA_I82801JI_S1 0x3a208086
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#define ATA_I82801JI_S2 0x3a268086
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#define ATA_5Series_S1 0x3b208086
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#define ATA_5Series_S2 0x3b218086
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#define ATA_5Series_S3 0x3b268086
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#define ATA_5Series_S4 0x3b288086
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#define ATA_5Series_S5 0x3b2d8086
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#define ATA_5Series_S6 0x3b2e8086
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#define ATA_IBP_S1 0x3b208086
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#define ATA_IBP_S2 0x3b218086
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#define ATA_IBP_S3 0x3b268086
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#define ATA_IBP_S4 0x3b288086
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#define ATA_IBP_S5 0x3b2d8086
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#define ATA_IBP_S6 0x3b2e8086
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#define ATA_CPT_S1 0x1c008086
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#define ATA_CPT_S2 0x1c018086
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@ -149,12 +149,12 @@ ata_intel_probe(device_t dev)
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{ ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
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{ ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
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{ ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
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{ ATA_IBP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak" },
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{ ATA_IBP_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" },
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{ ATA_IBP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak" },
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{ ATA_IBP_S4, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" },
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{ ATA_IBP_S5, 0, INTEL_6CH2, 0, ATA_SA300, "Ibex Peak-M" },
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{ ATA_IBP_S6, 0, INTEL_6CH, 0, ATA_SA300, "Ibex Peak-M" },
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{ ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" },
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{ ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA600, "Cougar Point" },
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{ ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
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@ -106,8 +106,8 @@ static const struct {
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{ HDA_INTEL_82801I, "Intel 82801I", 0, 0 },
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{ HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 },
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{ HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 },
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{ HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 },
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{ HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 },
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{ HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 },
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{ HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 },
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{ HDA_INTEL_SCH, "Intel SCH", 0, 0 },
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{ HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI },
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{ HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI },
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