Fix AR5416 and later parts when building with AH_DEBUG or similar defined:
always define OS_REG_UNSWAPPED and use it in ath_hal_reg_{read,write}. Approved by: re (kib)
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@ -254,7 +254,7 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
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}
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}
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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if (OS_REG_UNSWAPPED(reg))
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bus_space_write_4(tag, h, reg, val);
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else
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#endif
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@ -269,7 +269,7 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
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u_int32_t val;
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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if (OS_REG_UNSWAPPED(reg))
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val = bus_space_read_4(tag, h, reg);
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else
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#endif
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@ -320,7 +320,7 @@ ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
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bus_space_handle_t h = ah->ah_sh;
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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if (OS_REG_UNSWAPPED(reg))
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bus_space_write_4(tag, h, reg, val);
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else
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#endif
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@ -335,7 +335,7 @@ ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
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u_int32_t val;
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (reg >= 0x4000 && reg < 0x5000)
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if (OS_REG_UNSWAPPED(reg))
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val = bus_space_read_4(tag, h, reg);
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else
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#endif
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@ -68,15 +68,27 @@ typedef bus_space_handle_t HAL_BUS_HANDLE;
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struct ath_hal;
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/*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to explicitly byte-swap those registers.
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* OS_REG_UNSWAPPED identifies the registers that need special handling.
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*/
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_UNSWAPPED(_reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
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((_reg) >= 0x7000 && (_reg) < 0x8000))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_UNSWAPPED(_reg) (0)
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#endif /* _BYTE_ORDER */
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/*
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* Register read/write operations are either handled through
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* platform-dependent routines (or when debugging is enabled
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* with AH_DEBUG); or they are inline expanded using the macros
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* defined below. For public builds we inline expand only for
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* platforms where it is certain what the requirements are to
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* read/write registers--typically they are memory-mapped and
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* no explicit synchronization or memory invalidation operations
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* are required (e.g. i386).
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* defined below.
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*/
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#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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@ -94,13 +106,7 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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* Most of this code is collapsed at compile time because the
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* register values are constants.
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*/
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#define AH_LITTLE_ENDIAN 1234
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#define AH_BIG_ENDIAN 4321
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#if _BYTE_ORDER == _BIG_ENDIAN
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#define OS_REG_UNSWAPPED(_reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) || \
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((_reg) >= 0x7000 && (_reg) < 0x8000))
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#define OS_REG_WRITE(_ah, _reg, _val) do { \
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if (OS_REG_UNSWAPPED(_reg)) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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@ -116,7 +122,6 @@ extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg)))
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#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
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#define OS_REG_UNSWAPPED(_reg) (0)
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
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(bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
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