Remove the ncr(4) drive.
This driver has been obsolete since the FreeBSD 4.x. It should have been removed then since the sym(4) driver had subsumed it. The driver was commented out of GENERIC in 2000. RelNotes: Yes
This commit is contained in:
Warner Losh
parent
51a2f83991
commit
6a18678249
@ -304,7 +304,6 @@ MAN= aac.4 \
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my.4 \
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nand.4 \
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nandsim.4 \
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ncr.4 \
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${_ndis.4} \
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net80211.4 \
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netdump.4 \
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@ -1,82 +0,0 @@
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.\"
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.\" Copyright (c) 1994 James A. Jegers
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. The name of the author may not be used to endorse or promote products
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.\" derived from this software without specific prior written permission
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd August 19, 2004
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.Dt NCR 4
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.Os
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.Sh NAME
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.Nm ncr
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.Nd NCR 53C8xx SCSI driver
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device pci"
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.Cd "device scbus"
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.Cd "device ncr"
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.Ed
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.Sh HARDWARE
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The
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.Nm
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driver provides support for the following NCR/Symbios SCSI controller
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chips:
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.Pp
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.Bl -bullet -compact
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.It
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.Tn 53C810
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.It
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.Tn 53C810A
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.It
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.Tn 53C815
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.It
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.Tn 53C820
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.It
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.Tn 53C825A
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.It
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.Tn 53C860
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.It
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.Tn 53C875
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.It
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.Tn 53C875J
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.It
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.Tn 53C885
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.It
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.Tn 53C895
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.It
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.Tn 53C895A
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.It
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.Tn 53C896
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.It
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.Tn 53C1510D
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.El
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.Sh SEE ALSO
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.Xr cd 4 ,
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.Xr ch 4 ,
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.Xr da 4 ,
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.Xr intro 4 ,
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.Xr sa 4 ,
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.Xr scsi 4 ,
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.Xr sym 4
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@ -159,53 +159,6 @@ permanent PCI parity errors detected.
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This option is supplied for
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convenience but it is neither recommended nor supported.
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.Pp
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The generic
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.Xr ncr 4
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driver also supports SYM53C8XX based PCI SCSI controllers,
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except for the SYM53C1010, which is only supported by the
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.Nm
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driver.
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.Pp
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By default, when both the
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.Xr ncr 4
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and
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.Nm
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drivers are configured, the
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.Nm
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driver takes precedence over the
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.Xr ncr 4
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driver.
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The user can indicate a balancing of chip types between the two drivers
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by defining the
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.Ar SYM_SETUP_LP_PROBE_MAP
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kernel configuration option as follows:
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.Bl -column "0x40"
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.It Em "Bit Devices to be attached by ncr instead"
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.It "0x01 53C810a, 53C860"
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.It "0x02 53C825a, 53C875, 53C876, 53C885, 53C895"
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.It "0x04 53C895a, 53C896, 53C897, 53C1510d"
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.It "0x40 53C810, 53C815, 53C825"
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.El
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.Pp
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For example, if
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.Ar SYM_SETUP_LP_PROBE_MAP
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is supplied with the value 0x41, the
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.Xr ncr 4
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driver will attach to 53C810, 53C815, 53C825, 53C810a, and 53C860 based
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controllers,
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and the
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.Nm
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driver will attach to all other 53C8XX based controllers.
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.Pp
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When only the
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.Nm
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driver is configured, the
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.Ar SYM_SETUP_LP_PROBE_MAP
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option has no effect.
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Thus, in this case, the
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.Nm
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driver will attach all 53C8XX based controllers present in the system.
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.Pp
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This driver offers other options
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that are not currently exported to the user.
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They are defined and documented in the
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@ -342,7 +295,6 @@ The DEC KZPCA-AA is a rebadged SYM8952U.
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.Sh SEE ALSO
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.Xr cd 4 ,
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.Xr da 4 ,
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.Xr ncr 4 ,
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.Xr sa 4 ,
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.Xr scsi 4 ,
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.Xr camcontrol 8
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@ -139,8 +139,7 @@ device isp # Qlogic family
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device mpt # LSI-Logic MPT-Fusion
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device mps # LSI-Logic MPT-Fusion 2
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device mpr # LSI-Logic MPT-Fusion 3
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#device ncr # NCR/Symbios Logic
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device sym # NCR/Symbios Logic (newer chipsets + those of `ncr')
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device sym # NCR/Symbios Logic
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device trm # Tekram DC395U/UW/F DC315U adapters
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device isci # Intel C600 SAS controller
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device ocs_fc # Emulex FC adapters
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@ -1563,7 +1563,6 @@ options TERMINAL_KERN_ATTR=(FG_LIGHTRED|BG_BLACK)
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# ispfw: Firmware module for Qlogic host adapters
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# mpt: LSI-Logic MPT/Fusion 53c1020 or 53c1030 Ultra4
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# or FC9x9 Fibre Channel host adapters.
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# ncr: NCR 53C810, 53C825 self-contained SCSI host adapters.
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# sym: Symbios/Logic 53C8XX family of PCI-SCSI I/O processors:
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# 53C810, 53C810A, 53C815, 53C825, 53C825A, 53C860, 53C875,
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# 53C876, 53C885, 53C895, 53C895A, 53C896, 53C897, 53C1510D,
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@ -1592,7 +1591,6 @@ hint.isp.0.portwnn="w50000000aaaa0000"
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hint.isp.0.nodewnn="w50000000aaaa0001"
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device ispfw
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device mpt
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device ncr
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device sym
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device trm
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@ -1650,12 +1648,6 @@ options ISP_TARGET_MODE=1
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#
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options ISP_DEFAULT_ROLES=0
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# Options used in dev/sym/ (Symbios SCSI driver).
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#options SYM_SETUP_LP_PROBE_MAP #-Low Priority Probe Map (bits)
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# Allows the ncr to take precedence
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# 1 (1<<0) -> 810a, 860
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# 2 (1<<1) -> 825a, 875, 885, 895
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# 4 (1<<2) -> 895a, 896, 1510d
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#options SYM_SETUP_SCSI_DIFF #-HVD support for 825a, 875, 885
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# disabled:0 (default), enabled:1
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#options SYM_SETUP_PCI_PARITY #-PCI parity checking
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@ -2923,11 +2915,6 @@ options MSGTQL=41 # Max number of messages in system
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options NBUF=512 # Number of buffer headers
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options SCSI_NCR_DEBUG
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options SCSI_NCR_MAX_SYNC=10000
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options SCSI_NCR_MAX_WIDE=1
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options SCSI_NCR_MYADDR=7
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options SC_DEBUG_LEVEL=5 # Syscons debug level
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options SC_RENDER_DEBUG # syscons rendering debugging
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@ -2509,7 +2509,6 @@ dev/nand/nandsim_ctrl.c optional nandsim nand
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dev/nand/nandsim_log.c optional nandsim nand
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dev/nand/nandsim_swap.c optional nandsim nand
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dev/nand/nfc_if.m optional nand
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dev/ncr/ncr.c optional ncr pci
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dev/netmap/if_ptnet.c optional netmap inet
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dev/netmap/netmap.c optional netmap
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dev/netmap/netmap_freebsd.c optional netmap
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@ -386,12 +386,6 @@ SYM_SETUP_PCI_PARITY opt_sym.h #-PCI parity checking
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SYM_SETUP_MAX_LUN opt_sym.h #-Number of LUNs supported
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# default:8, range:[1..64]
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# Options used only in dev/ncr/*
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SCSI_NCR_DEBUG opt_ncr.h
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SCSI_NCR_MAX_SYNC opt_ncr.h
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SCSI_NCR_MAX_WIDE opt_ncr.h
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SCSI_NCR_MYADDR opt_ncr.h
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# Options used only in dev/isp/*
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ISP_TARGET_MODE opt_isp.h
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ISP_FW_CRASH_DUMP opt_isp.h
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@ -1,45 +0,0 @@
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#!/usr/bin/perl -w
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# $FreeBSD$
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use strict;
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if (!defined($ARGV[0])) {
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print(
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"
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Perl script to convert NCR script address into label+offset.
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Useful to find the failed NCR instruction ...
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usage: $0 <address>
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");
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exit(1);
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}
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my $errpos = hex($ARGV[0])/4;
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my $ofs=0;
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open (INPUT, "cc -E ncr.c 2>/dev/null |");
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while ($_ = <INPUT>)
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{
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last if /^struct script \{/;
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}
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while ($_ = <INPUT>)
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{
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last if /^\}\;/;
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my ($label, $size) = /ncrcmd\s+(\S+)\s+\[([^]]+)/;
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$size = eval($size);
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if (defined($label) && $label) {
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if ($errpos) {
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if ($ofs + $size > $errpos) {
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printf ("%4x: %s\n", $ofs * 4, $label);
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printf ("%4x: %s + %d\n", $errpos * 4, $label, $errpos - $ofs);
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last;
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}
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$ofs += $size;
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} else {
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printf ("%4x: %s\n", $ofs * 4, $label);
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}
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}
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}
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7118
sys/dev/ncr/ncr.c
7118
sys/dev/ncr/ncr.c
File diff suppressed because it is too large
Load Diff
@ -1,574 +0,0 @@
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/**************************************************************************
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**
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** $FreeBSD$
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**
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** Device driver for the NCR 53C810 PCI-SCSI-Controller.
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**
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** 386bsd / FreeBSD / NetBSD
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**
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**-------------------------------------------------------------------------
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**
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** Written for 386bsd and FreeBSD by
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** wolf@cologne.de Wolfgang Stanglmeier
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** se@mi.Uni-Koeln.de Stefan Esser
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**
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** Ported to NetBSD by
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** mycroft@gnu.ai.mit.edu
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**
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**-------------------------------------------------------------------------
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*/
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/*-
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** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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***************************************************************************
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*/
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#ifndef __NCR_REG_H__
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#define __NCR_REG_H__
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/*-----------------------------------------------------------------
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**
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** The ncr 53c810 register structure.
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**
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**-----------------------------------------------------------------
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*/
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struct ncr_reg {
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/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
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/*01*/ u_char nc_scntl1; /* no reset */
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#define ISCON 0x10 /* connected to scsi */
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#define CRST 0x08 /* force reset */
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/*02*/ u_char nc_scntl2; /* no disconnect expected */
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#define SDU 0x80 /* cmd: disconnect will raise error */
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#define CHM 0x40 /* sta: chained mode */
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#define WSS 0x08 /* sta: wide scsi send [W]*/
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#define WSR 0x01 /* sta: wide scsi received [W]*/
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/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
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#define EWS 0x08 /* cmd: enable wide scsi [W]*/
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/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
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#define RRE 0x40 /* r/w:e enable response to resel. */
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#define SRE 0x20 /* r/w:e enable response to select */
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/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
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/*06*/ u_char nc_sdid; /* ### Destination-ID */
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/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
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/*08*/ u_char nc_sfbr; /* ### First byte in phase */
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/*09*/ u_char nc_socl;
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#define CREQ 0x80 /* r/w: SCSI-REQ */
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#define CACK 0x40 /* r/w: SCSI-ACK */
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#define CBSY 0x20 /* r/w: SCSI-BSY */
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#define CSEL 0x10 /* r/w: SCSI-SEL */
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#define CATN 0x08 /* r/w: SCSI-ATN */
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#define CMSG 0x04 /* r/w: SCSI-MSG */
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#define CC_D 0x02 /* r/w: SCSI-C_D */
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#define CI_O 0x01 /* r/w: SCSI-I_O */
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/*0a*/ u_char nc_ssid;
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/*0b*/ u_char nc_sbcl;
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/*0c*/ u_char nc_dstat;
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#define DFE 0x80 /* sta: dma fifo empty */
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#define MDPE 0x40 /* int: master data parity error */
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#define BF 0x20 /* int: script: bus fault */
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#define ABRT 0x10 /* int: script: command aborted */
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#define SSI 0x08 /* int: script: single step */
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#define SIR 0x04 /* int: script: interrupt instruct. */
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#define IID 0x01 /* int: script: illegal instruct. */
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/*0d*/ u_char nc_sstat0;
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#define ILF 0x80 /* sta: data in SIDL register lsb */
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#define ORF 0x40 /* sta: data in SODR register lsb */
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#define OLF 0x20 /* sta: data in SODL register lsb */
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#define AIP 0x10 /* sta: arbitration in progress */
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#define LOA 0x08 /* sta: arbitration lost */
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#define WOA 0x04 /* sta: arbitration won */
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#define IRST 0x02 /* sta: scsi reset signal */
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#define SDP 0x01 /* sta: scsi parity signal */
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/*0e*/ u_char nc_sstat1;
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#define FF3210 0xf0 /* sta: bytes in the scsi fifo */
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/*0f*/ u_char nc_sstat2;
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#define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
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#define ORF1 0x40 /* sta: data in SODR register msb[W]*/
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#define OLF1 0x20 /* sta: data in SODL register msb[W]*/
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#define LDSC 0x02 /* sta: disconnect & reconnect */
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/*10*/ u_int32_t nc_dsa; /* --> Base page */
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/*14*/ u_char nc_istat; /* --> Main Command and status */
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#define CABRT 0x80 /* cmd: abort current operation */
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#define SRST 0x40 /* mod: reset chip */
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#define SIGP 0x20 /* r/w: message from host to ncr */
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#define SEM 0x10 /* r/w: message between host + ncr */
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#define CON 0x08 /* sta: connected to scsi */
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#define INTF 0x04 /* sta: int on the fly (reset by wr)*/
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#define SIP 0x02 /* sta: scsi-interrupt */
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#define DIP 0x01 /* sta: host/script interrupt */
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/*15*/ u_char nc_15_;
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/*16*/ u_char nc_16_;
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/*17*/ u_char nc_17_;
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/*18*/ u_char nc_ctest0;
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/*19*/ u_char nc_ctest1;
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/*1a*/ u_char nc_ctest2;
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#define CSIGP 0x40
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/*1b*/ u_char nc_ctest3;
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#define FLF 0x08 /* cmd: flush dma fifo */
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#define CLF 0x04 /* cmd: clear dma fifo */
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#define FM 0x02 /* mod: fetch pin mode */
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#define WRIE 0x01 /* mod: write and invalidate enable */
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/*1c*/ u_int32_t nc_temp; /* ### Temporary stack */
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/*20*/ u_char nc_dfifo;
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/*21*/ u_char nc_ctest4;
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#define BDIS 0x80 /* mod: burst disable */
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#define MPEE 0x08 /* mod: master parity error enable */
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|
||||
/*22*/ u_char nc_ctest5;
|
||||
#define DFS 0x20 /* mod: dma fifo size */
|
||||
/*23*/ u_char nc_ctest6;
|
||||
|
||||
/*24*/ u_int32_t nc_dbc; /* ### Byte count and command */
|
||||
/*28*/ u_int32_t nc_dnad; /* ### Next command register */
|
||||
/*2c*/ u_int32_t nc_dsp; /* --> Script Pointer */
|
||||
/*30*/ u_int32_t nc_dsps; /* --> Script pointer save/opcode#2 */
|
||||
/*34*/ u_int32_t nc_scratcha; /* ??? Temporary register a */
|
||||
|
||||
/*38*/ u_char nc_dmode;
|
||||
#define BL_2 0x80 /* mod: burst length shift value +2 */
|
||||
#define BL_1 0x40 /* mod: burst length shift value +1 */
|
||||
#define ERL 0x08 /* mod: enable read line */
|
||||
#define ERMP 0x04 /* mod: enable read multiple */
|
||||
#define BOF 0x02 /* mod: burst op code fetch */
|
||||
|
||||
/*39*/ u_char nc_dien;
|
||||
/*3a*/ u_char nc_dwt;
|
||||
|
||||
/*3b*/ u_char nc_dcntl; /* --> Script execution control */
|
||||
#define CLSE 0x80 /* mod: cache line size enable */
|
||||
#define PFF 0x40 /* cmd: pre-fetch flush */
|
||||
#define PFEN 0x20 /* mod: pre-fetch enable */
|
||||
#define SSM 0x10 /* mod: single step mode */
|
||||
#define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
|
||||
#define STD 0x04 /* cmd: start dma mode */
|
||||
#define IRQD 0x02 /* mod: irq disable */
|
||||
#define NOCOM 0x01 /* cmd: protect sfbr while reselect */
|
||||
|
||||
/*3c*/ u_int32_t nc_adder;
|
||||
|
||||
/*40*/ u_short nc_sien; /* -->: interrupt enable */
|
||||
/*42*/ u_short nc_sist; /* <--: interrupt status */
|
||||
#define STO 0x0400/* sta: timeout (select) */
|
||||
#define GEN 0x0200/* sta: timeout (general) */
|
||||
#define HTH 0x0100/* sta: timeout (handshake) */
|
||||
#define MA 0x80 /* sta: phase mismatch */
|
||||
#define CMP 0x40 /* sta: arbitration complete */
|
||||
#define SEL 0x20 /* sta: selected by another device */
|
||||
#define RSL 0x10 /* sta: reselected by another device*/
|
||||
#define SGE 0x08 /* sta: gross error (over/underflow)*/
|
||||
#define UDC 0x04 /* sta: unexpected disconnect */
|
||||
#define RST 0x02 /* sta: scsi bus reset detected */
|
||||
#define PAR 0x01 /* sta: scsi parity error */
|
||||
|
||||
/*44*/ u_char nc_slpar;
|
||||
/*45*/ u_char nc_swide;
|
||||
/*46*/ u_char nc_macntl;
|
||||
/*47*/ u_char nc_gpcntl;
|
||||
/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
|
||||
/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
|
||||
/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
|
||||
|
||||
/*4c*/ u_char nc_stest0;
|
||||
|
||||
/*4d*/ u_char nc_stest1;
|
||||
#define DBLEN 0x08 /* clock doubler running */
|
||||
#define DBLSEL 0x04 /* clock doubler selected */
|
||||
|
||||
/*4e*/ u_char nc_stest2;
|
||||
#define ROF 0x40 /* reset scsi offset (after gross error!) */
|
||||
#define EXT 0x02 /* extended filtering */
|
||||
|
||||
/*4f*/ u_char nc_stest3;
|
||||
#define TE 0x80 /* c: tolerAnt enable */
|
||||
#define HSC 0x20 /* c: Halt SCSI Clock */
|
||||
#define CSF 0x02 /* c: clear scsi fifo */
|
||||
|
||||
/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
|
||||
/*52*/ u_char nc_stest4;
|
||||
#define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
|
||||
#define SMODE_HVD 0x40 /* High Voltage Differential */
|
||||
#define SMODE_SE 0x80 /* Single Ended */
|
||||
#define SMODE_LVD 0xc0 /* Low Voltage Differential */
|
||||
#define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
|
||||
|
||||
/*53*/ u_char nc_53_;
|
||||
/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
|
||||
/*56*/ u_short nc_56_;
|
||||
/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
|
||||
/*5a*/ u_short nc_5a_;
|
||||
/*5c*/ u_char nc_scr0; /* Working register B */
|
||||
/*5d*/ u_char nc_scr1; /* */
|
||||
/*5e*/ u_char nc_scr2; /* */
|
||||
/*5f*/ u_char nc_scr3; /* */
|
||||
/*60*/
|
||||
};
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Utility macros for the script.
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
|
||||
#define REG(r) REGJ (nc_, r)
|
||||
|
||||
#ifndef TARGET_MODE
|
||||
#define TARGET_MODE 0
|
||||
#endif
|
||||
|
||||
typedef u_int32_t ncrcmd;
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** SCSI phases
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_DATA_OUT 0x00000000
|
||||
#define SCR_DATA_IN 0x01000000
|
||||
#define SCR_COMMAND 0x02000000
|
||||
#define SCR_STATUS 0x03000000
|
||||
#define SCR_ILG_OUT 0x04000000
|
||||
#define SCR_ILG_IN 0x05000000
|
||||
#define SCR_MSG_OUT 0x06000000
|
||||
#define SCR_MSG_IN 0x07000000
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Data transfer via SCSI.
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** MOVE_ABS (LEN)
|
||||
** <<start address>>
|
||||
**
|
||||
** MOVE_IND (LEN)
|
||||
** <<dnad_offset>>
|
||||
**
|
||||
** MOVE_TBL
|
||||
** <<dnad_offset>>
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
|
||||
#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
|
||||
#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
|
||||
|
||||
struct scr_tblmove {
|
||||
u_int32_t size;
|
||||
u_int32_t addr;
|
||||
};
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Selection
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
|
||||
** <<alternate_address>>
|
||||
**
|
||||
** SEL_TBL | << dnad_offset>> [ | REL_JMP]
|
||||
** <<alternate_address>>
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_SEL_ABS 0x40000000
|
||||
#define SCR_SEL_ABS_ATN 0x41000000
|
||||
#define SCR_SEL_TBL 0x42000000
|
||||
#define SCR_SEL_TBL_ATN 0x43000000
|
||||
|
||||
struct scr_tblsel {
|
||||
u_char sel_0;
|
||||
u_char sel_sxfer;
|
||||
u_char sel_id;
|
||||
u_char sel_scntl3;
|
||||
};
|
||||
|
||||
#define SCR_JMP_REL 0x04000000
|
||||
#define SCR_ID(id) (((u_int32_t)(id)) << 16)
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Waiting for Disconnect or Reselect
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** WAIT_DISC
|
||||
** dummy: <<alternate_address>>
|
||||
**
|
||||
** WAIT_RESEL
|
||||
** <<alternate_address>>
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_WAIT_DISC 0x48000000
|
||||
#define SCR_WAIT_RESEL 0x50000000
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Bit Set / Reset
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** SET (flags {|.. })
|
||||
**
|
||||
** CLR (flags {|.. })
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_SET(f) (0x58000000 | (f))
|
||||
#define SCR_CLR(f) (0x60000000 | (f))
|
||||
|
||||
#define SCR_CARRY 0x00000400
|
||||
#define SCR_TRG 0x00000200
|
||||
#define SCR_ACK 0x00000040
|
||||
#define SCR_ATN 0x00000008
|
||||
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Memory to memory move
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** COPY (bytecount)
|
||||
** << source_address >>
|
||||
** << destination_address >>
|
||||
**
|
||||
** SCR_COPY sets the NO FLUSH option by default.
|
||||
** SCR_COPY_F does not set this option.
|
||||
**
|
||||
** For chips which do not support this option,
|
||||
** ncr_copy_and_bind() will remove this bit.
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_NO_FLUSH 0x01000000
|
||||
|
||||
#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
|
||||
#define SCR_COPY_F(n) (0xc0000000 | (n))
|
||||
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Register move and binary operations
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** SFBR_REG (reg, op, data) reg = SFBR op data
|
||||
** << 0 >>
|
||||
**
|
||||
** REG_SFBR (reg, op, data) SFBR = reg op data
|
||||
** << 0 >>
|
||||
**
|
||||
** REG_REG (reg, op, data) reg = reg op data
|
||||
** << 0 >>
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_REG_OFS(ofs) ((ofs) << 16ul)
|
||||
|
||||
#define SCR_SFBR_REG(reg,op,data) \
|
||||
(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
|
||||
|
||||
#define SCR_REG_SFBR(reg,op,data) \
|
||||
(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
|
||||
|
||||
#define SCR_REG_REG(reg,op,data) \
|
||||
(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
|
||||
|
||||
|
||||
#define SCR_LOAD 0x00000000
|
||||
#define SCR_SHL 0x01000000
|
||||
#define SCR_OR 0x02000000
|
||||
#define SCR_XOR 0x03000000
|
||||
#define SCR_AND 0x04000000
|
||||
#define SCR_SHR 0x05000000
|
||||
#define SCR_ADD 0x06000000
|
||||
#define SCR_ADDC 0x07000000
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** FROM_REG (reg) reg = SFBR
|
||||
** << 0 >>
|
||||
**
|
||||
** TO_REG (reg) SFBR = reg
|
||||
** << 0 >>
|
||||
**
|
||||
** LOAD_REG (reg, data) reg = <data>
|
||||
** << 0 >>
|
||||
**
|
||||
** LOAD_SFBR(data) SFBR = <data>
|
||||
** << 0 >>
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_FROM_REG(reg) \
|
||||
SCR_REG_SFBR(reg,SCR_OR,0)
|
||||
|
||||
#define SCR_TO_REG(reg) \
|
||||
SCR_SFBR_REG(reg,SCR_OR,0)
|
||||
|
||||
#define SCR_LOAD_REG(reg,data) \
|
||||
SCR_REG_REG(reg,SCR_LOAD,data)
|
||||
|
||||
#define SCR_LOAD_SFBR(data) \
|
||||
(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** Waiting for Disconnect or Reselect
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
**
|
||||
** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<address>>
|
||||
**
|
||||
** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<distance>>
|
||||
**
|
||||
** CALL [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<address>>
|
||||
**
|
||||
** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<distance>>
|
||||
**
|
||||
** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<dummy>>
|
||||
**
|
||||
** INT [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<ident>>
|
||||
**
|
||||
** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
|
||||
** <<ident>>
|
||||
**
|
||||
** Conditions:
|
||||
** WHEN (phase)
|
||||
** IF (phase)
|
||||
** CARRY
|
||||
** DATA (data, mask)
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define SCR_NO_OP 0x80000000
|
||||
#define SCR_JUMP 0x80080000
|
||||
#define SCR_JUMPR 0x80880000
|
||||
#define SCR_CALL 0x88080000
|
||||
#define SCR_CALLR 0x88880000
|
||||
#define SCR_RETURN 0x90080000
|
||||
#define SCR_INT 0x98080000
|
||||
#define SCR_INT_FLY 0x98180000
|
||||
|
||||
#define IFFALSE(arg) (0x00080000 | (arg))
|
||||
#define IFTRUE(arg) (0x00000000 | (arg))
|
||||
|
||||
#define WHEN(phase) (0x00030000 | (phase))
|
||||
#define IF(phase) (0x00020000 | (phase))
|
||||
|
||||
#define DATA(D) (0x00040000 | ((D) & 0xff))
|
||||
#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
|
||||
|
||||
#define CARRYSET (0x00200000)
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
**
|
||||
** SCSI constants.
|
||||
**
|
||||
**-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
** Messages
|
||||
*/
|
||||
#define M_X_MODIFY_DP (0x00)
|
||||
|
||||
/*
|
||||
** Status
|
||||
*/
|
||||
#define SCSI_STATUS_ILLEGAL (0xff)
|
||||
#define SCSI_STATUS_SENSE (0x80)
|
||||
|
||||
/*
|
||||
** Bits defining chip features.
|
||||
** For now only some of them are used, since we explicitely
|
||||
** deal with PCI device id and revision id.
|
||||
*/
|
||||
#define FE_LED0 (1<<0)
|
||||
#define FE_WIDE (1<<1)
|
||||
#define FE_ULTRA (1<<2)
|
||||
#define FE_ULTRA2 (1<<3)
|
||||
#define FE_DBLR (1<<4)
|
||||
#define FE_QUAD (1<<5)
|
||||
#define FE_ERL (1<<6)
|
||||
#define FE_CLSE (1<<7)
|
||||
#define FE_WRIE (1<<8)
|
||||
#define FE_ERMP (1<<9)
|
||||
#define FE_BOF (1<<10)
|
||||
#define FE_DFS (1<<11)
|
||||
#define FE_PFEN (1<<12)
|
||||
#define FE_LDSTR (1<<13)
|
||||
#define FE_RAM (1<<14)
|
||||
#define FE_CLK80 (1<<15)
|
||||
#define FE_DIFF (1<<16)
|
||||
#define FE_BIOS (1<<17)
|
||||
#define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
|
||||
#define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_ULTRA2|FE_DBLR|FE_QUAD|F_CLK80)
|
||||
#define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
|
||||
|
||||
#endif /*__NCR_REG_H__*/
|
||||
@ -132,8 +132,7 @@ device isp # Qlogic family
|
||||
device mpt # LSI-Logic MPT-Fusion
|
||||
device mps # LSI-Logic MPT-Fusion 2
|
||||
device mpr # LSI-Logic MPT-Fusion 3
|
||||
#device ncr # NCR/Symbios Logic
|
||||
device sym # NCR/Symbios Logic (newer chipsets + those of `ncr')
|
||||
device sym # NCR/Symbios Logic
|
||||
device trm # Tekram DC395U/UW/F DC315U adapters
|
||||
device isci # Intel C600 SAS controller
|
||||
|
||||
|
||||
@ -17,6 +17,5 @@ nodevice hptmv
|
||||
nodevice ida
|
||||
|
||||
# The following drivers don't work with PAE enabled.
|
||||
makeoptions WITHOUT_MODULES+="ncr pst"
|
||||
nodevice ncr
|
||||
makeoptions WITHOUT_MODULES+="pst"
|
||||
nodevice pst
|
||||
|
||||
@ -266,7 +266,6 @@ SUBDIR= \
|
||||
my \
|
||||
${_nandfs} \
|
||||
${_nandsim} \
|
||||
${_ncr} \
|
||||
${_nctgpio} \
|
||||
${_ndis} \
|
||||
${_netgraph} \
|
||||
@ -751,7 +750,6 @@ _cp= cp
|
||||
_glxiic= glxiic
|
||||
_glxsb= glxsb
|
||||
#_ibcs2= ibcs2
|
||||
_ncr= ncr
|
||||
_pcfclock= pcfclock
|
||||
_pst= pst
|
||||
_sbni= sbni
|
||||
|
||||
@ -1,9 +0,0 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/ncr
|
||||
|
||||
KMOD= ncr
|
||||
SRCS= ncr.c
|
||||
SRCS+= device_if.h bus_if.h pci_if.h opt_ncr.h opt_cam.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in New Issue
Block a user