update to return correct blocksize- these chips have a fixed irq rate, so
block size varies only with format and rate.
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175f26d6ed
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@ -39,6 +39,7 @@
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#define DS1_CHANS 4
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#define DS1_RECPRIMARY 0
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#define DS1_IRQHZ ((48000 << 8) / 256)
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struct pbank {
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volatile u_int32_t Format;
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@ -521,6 +522,12 @@ ds1pchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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static int
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ds1pchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
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{
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struct sc_pchinfo *ch = data;
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int drate;
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/* irq rate is fixed at 187.5hz */
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drate = ch->spd * sndbuf_getbps(ch->buffer);
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blocksize = (drate << 8) / DS1_IRQHZ;
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return blocksize;
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}
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@ -842,6 +849,7 @@ ds_init(struct sc_info *sc)
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ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff, 4);
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ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0x3fff3fff, 4);
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ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0x3fff3fff, 4);
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return 0;
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}
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