From 6cd492bcd4fd443b34ca7d29452b6278be860bb1 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Mon, 11 Nov 2019 21:59:20 +0000 Subject: [PATCH] amd64: Issue MFENCE on context switch on AMD CPUs when reusing address space. On some AMD CPUs, in particular, machines that do not implement CLFLUSHOPT but do provide CLFLUSH, the CLFLUSH instruction is only synchronized with MFENCE. Code using CLFLUSH typicall needs to brace it with MFENCE both before and after flush, see for instance pmap_invalidate_cache_range(). If context switch occurs while inside the protected region, we need to ensure visibility of flushes done on the old CPU, to new CPU. For all other machines, locked operation done to lock switched thread, should be enough. For case of different address spaces, reload of %cr3 is serializing. Reviewed by: cem, jhb, scottph Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D22007 --- sys/amd64/amd64/pmap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index 226e2c3cbf12..9a8be3083e07 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -8810,8 +8810,11 @@ pmap_activate_sw(struct thread *td) oldpmap = PCPU_GET(curpmap); pmap = vmspace_pmap(td->td_proc->p_vmspace); - if (oldpmap == pmap) + if (oldpmap == pmap) { + if (cpu_vendor_id != CPU_VENDOR_INTEL) + mfence(); return; + } cpuid = PCPU_GET(cpuid); #ifdef SMP CPU_SET_ATOMIC(cpuid, &pmap->pm_active);