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MFp4: get the code that set the pc correctly to work, remove a few IQ31244

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specific mappings from locore.S, re-organize iq31244_machdep.c to work with
the new locore.S

Spotted out by:	jmg
This commit is contained in:
Olivier Houchard 2005-02-20 21:34:59 +00:00
parent 509cfe6fb0
commit 6d4b3b4cb5
2 changed files with 22 additions and 21 deletions
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21
sys/arm/arm/locore.S
View File

@ -164,16 +164,19 @@ mmu_done:
ldr r4, =KERNVIRTADDR
cmp pc, r4
#if KERNVIRTADDR > KERNPHYSADDR
ldrlt r4, =KERNVIRTADDR
ldrlt r5, =KERNPHYSADDR
sublt r4, r4, r5
addlt pc, pc, r4
bgt virt_done
ldr r4, =KERNVIRTADDR
ldr r5, =KERNPHYSADDR
sub r4, r4, r5
add pc, pc, r4
#else
ldrgt r4, =KERNPHYSADDR
ldrgt r5, =KERNVIRTADDR
subgt r4, r4, r5
sublt pc, pc, r4
blt virt_done
ldr r4, =KERNPHYSADDR
ldr r5, =KERNVIRTADDR
sub r4, r4, r5
sub pc, pc, r4
#endif
virt_done:
ldr fp, =KERNVIRTADDR /* trace back starts here */
bl _C_LABEL(initarm) /* Off we go */
@ -195,12 +198,10 @@ Lstartup_pagetable:
.word STARTUP_PAGETABLE_ADDR
mmu_init_table:
/* fill all table VA==PA */
MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
/* map SDRAM VA==PA, WT cacheable */
MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
/* map VA 0xc0000000..0xc3ffffff to PA */
MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
MMU_INIT(0xfe800000, 0xfe800000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
.word 0 /* end of table */
#endif

22
sys/arm/xscale/i80321/iq31244_machdep.c
View File

@ -209,16 +209,9 @@ initarm(void *arg, void *arg2)
uint32_t fake_preload[35];
uint32_t memsize, memstart;
i80321_calibrate_delay();
cninit();
i = 0;
set_cpufuncs();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_sdram_bounds(&obio_bs_tag, VERDE_PMMR_BASE + VERDE_MCU_BASE,
&memstart, &memsize);
fake_preload[i++] = MODINFO_NAME;
fake_preload[i++] = strlen("elf kernel") + 1;
strcpy((char*)&fake_preload[i++], "elf kernel");
@ -237,7 +230,6 @@ initarm(void *arg, void *arg2)
fake_preload[i] = 0;
preload_metadata = (void *)fake_preload;
physmem = memsize / PAGE_SIZE;
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -308,7 +300,6 @@ initarm(void *arg, void *arg2)
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
@ -400,7 +391,6 @@ initarm(void *arg, void *arg2)
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
@ -409,6 +399,7 @@ initarm(void *arg, void *arg2)
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
@ -430,6 +421,15 @@ initarm(void *arg, void *arg2)
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_calibrate_delay();
i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
&memstart, &memsize);
physmem = memsize / PAGE_SIZE;
cninit();
/* Set stack for exception handlers */