d/freebsd-nq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Go ahead and disable the interrupts for the DBGU the boot loader may

Browse Source 
have left enabled after we detect the CPU, and remove the multiplely
copied code from the SoC modules.
This commit is contained in:
Warner Losh 2012-07-10 19:48:42 +00:00
parent 0f078d635e
commit 6e21b3a1b6
5 changed files with 9 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
sys/arm/at91/at91_machdep.c
View File

@ -90,6 +90,7 @@ __FBSDID("$FreeBSD$");
#include <arm/at91/at91board.h> #include <arm/at91/at91board.h>
#include <arm/at91/at91var.h> #include <arm/at91/at91var.h>
#include <arm/at91/at91_usartreg.h>
#include <arm/at91/at91rm92reg.h> #include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91sam9g20reg.h> #include <arm/at91/at91sam9g20reg.h>
@ -382,6 +383,14 @@ at91_try_id(uint32_t dbgu_base)
default: default:
break; break;
} }
/*
* Disable interrupts
*/
*(volatile uint32_t *)(AT91_BASE + dbgu_base + USART_IDR) = 0xffffffff;
/*
* Save the name for later...
*/
snprintf(soc_data.name, sizeof(soc_data.name), "%s%s%s", snprintf(soc_data.name, sizeof(soc_data.name), "%s%s%s",
soc_type_name[soc_data.type], soc_type_name[soc_data.type],
soc_data.subtype == AT91_ST_NONE ? "" : " subtype ", soc_data.subtype == AT91_ST_NONE ? "" : " subtype ",

8
sys/arm/at91/at91rm9200.c
View File

@ -50,7 +50,6 @@ struct at91rm92_softc {
bus_space_handle_t sc_sh; bus_space_handle_t sc_sh;
bus_space_handle_t sc_sys_sh; bus_space_handle_t sc_sys_sh;
bus_space_handle_t sc_aic_sh; bus_space_handle_t sc_aic_sh;
bus_space_handle_t sc_dbg_sh;
bus_space_handle_t sc_matrix_sh; bus_space_handle_t sc_matrix_sh;
}; };
/* /*
@ -194,10 +193,6 @@ at91_attach(device_t dev)
AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_DBGU_BASE,
AT91RM92_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
panic("Enable to map DBGU registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE, if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE,
AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0) AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
@ -229,9 +224,6 @@ at91_attach(device_t dev)
/* Disable all interrupts for the SDRAM controller */ /* Disable all interrupts for the SDRAM controller */
bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff);
/* Disable all interrupts for DBGU */
bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
/* Update USB device port clock info */ /* Update USB device port clock info */
clk = at91_pmc_clock_ref("udpck"); clk = at91_pmc_clock_ref("udpck");
clk->pmc_mask = PMC_SCER_UDP; clk->pmc_mask = PMC_SCER_UDP;

8
sys/arm/at91/at91sam9260.c
View File

@ -50,7 +50,6 @@ struct at91sam9_softc {
bus_space_handle_t sc_sh; bus_space_handle_t sc_sh;
bus_space_handle_t sc_sys_sh; bus_space_handle_t sc_sys_sh;
bus_space_handle_t sc_aic_sh; bus_space_handle_t sc_aic_sh;
bus_space_handle_t sc_dbg_sh;
bus_space_handle_t sc_matrix_sh; bus_space_handle_t sc_matrix_sh;
}; };
@ -194,10 +193,6 @@ at91_attach(device_t dev)
AT91SAM9260_SYS_SIZE, &sc->sc_sys_sh) != 0) AT91SAM9260_SYS_SIZE, &sc->sc_sys_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_DBGU_BASE,
AT91SAM9260_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
panic("Enable to map DBGU registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_AIC_BASE, if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9260_AIC_BASE,
AT91SAM9260_AIC_SIZE, &sc->sc_aic_sh) != 0) AT91SAM9260_AIC_SIZE, &sc->sc_aic_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
@ -223,9 +218,6 @@ at91_attach(device_t dev)
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
/* Disable all interrupts for DBGU */
bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
if (bus_space_subregion(sc->sc_st, sc->sc_sh, if (bus_space_subregion(sc->sc_st, sc->sc_sh,
AT91SAM9260_MATRIX_BASE, AT91SAM9260_MATRIX_SIZE, AT91SAM9260_MATRIX_BASE, AT91SAM9260_MATRIX_SIZE,
&sc->sc_matrix_sh) != 0) &sc->sc_matrix_sh) != 0)

8
sys/arm/at91/at91sam9g20.c
View File

@ -50,7 +50,6 @@ struct at91sam9_softc {
bus_space_handle_t sc_sh; bus_space_handle_t sc_sh;
bus_space_handle_t sc_sys_sh; bus_space_handle_t sc_sys_sh;
bus_space_handle_t sc_aic_sh; bus_space_handle_t sc_aic_sh;
bus_space_handle_t sc_dbg_sh;
bus_space_handle_t sc_matrix_sh; bus_space_handle_t sc_matrix_sh;
}; };
@ -205,10 +204,6 @@ at91_attach(device_t dev)
AT91SAM9G20_SYS_SIZE, &sc->sc_sys_sh) != 0) AT91SAM9G20_SYS_SIZE, &sc->sc_sys_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_DBGU_BASE,
AT91SAM9G20_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
panic("Enable to map DBGU registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_AIC_BASE, if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9G20_AIC_BASE,
AT91SAM9G20_AIC_SIZE, &sc->sc_aic_sh) != 0) AT91SAM9G20_AIC_SIZE, &sc->sc_aic_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
@ -234,9 +229,6 @@ at91_attach(device_t dev)
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
/* Disable all interrupts for DBGU */
bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
if (bus_space_subregion(sc->sc_st, sc->sc_sh, if (bus_space_subregion(sc->sc_st, sc->sc_sh,
AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE, AT91SAM9G20_MATRIX_BASE, AT91SAM9G20_MATRIX_SIZE,
&sc->sc_matrix_sh) != 0) &sc->sc_matrix_sh) != 0)

8
sys/arm/at91/at91sam9x25.c
View File

@ -50,7 +50,6 @@ struct at91sam9x25_softc {
bus_space_handle_t sc_sh; bus_space_handle_t sc_sh;
bus_space_handle_t sc_sys_sh; bus_space_handle_t sc_sys_sh;
bus_space_handle_t sc_aic_sh; bus_space_handle_t sc_aic_sh;
bus_space_handle_t sc_dbg_sh;
bus_space_handle_t sc_matrix_sh; bus_space_handle_t sc_matrix_sh;
}; };
@ -208,10 +207,6 @@ at91_attach(device_t dev)
AT91SAM9X25_SYS_SIZE, &sc->sc_sys_sh) != 0) AT91SAM9X25_SYS_SIZE, &sc->sc_sys_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_DBGU_BASE,
AT91SAM9X25_DBGU_SIZE, &sc->sc_dbg_sh) != 0)
panic("Enable to map DBGU registers");
if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_AIC_BASE, if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91SAM9X25_AIC_BASE,
AT91SAM9X25_AIC_SIZE, &sc->sc_aic_sh) != 0) AT91SAM9X25_AIC_SIZE, &sc->sc_aic_sh) != 0)
panic("Enable to map system registers"); panic("Enable to map system registers");
@ -237,9 +232,6 @@ at91_attach(device_t dev)
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff);
bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff);
/* Disable all interrupts for DBGU */
bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff);
if (bus_space_subregion(sc->sc_st, sc->sc_sh, if (bus_space_subregion(sc->sc_st, sc->sc_sh,
AT91SAM9X25_MATRIX_BASE, AT91SAM9X25_MATRIX_SIZE, AT91SAM9X25_MATRIX_BASE, AT91SAM9X25_MATRIX_SIZE,
&sc->sc_matrix_sh) != 0) &sc->sc_matrix_sh) != 0)