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arm64: rockchip: rk_clk_pll: Check mode on recalc

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If the pll is in slow or deep slow mode return the correct frequency.
This commit is contained in:
Emmanuel Vadot 2019-09-30 15:01:09 +00:00
parent d46c04051d
commit 6e5eac8cc0
1 changed files with 16 additions and 1 deletions
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17
sys/arm64/rockchip/clk/rk_clk_pll.c
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@ -367,7 +367,7 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
uint32_t postdiv1, postdiv2, fracdiv;
uint32_t con1, con2, con3, con4;
uint64_t foutvco;
uint32_t mode;
sc = clknode_get_softc(clk);
DEVICE_LOCK(clk);
@ -377,6 +377,21 @@ rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
READ4(clk, sc->base_offset + 0xC, &con4);
DEVICE_UNLOCK(clk);
/*
* if we are in slow mode the output freq
* is the parent one, the 24Mhz external oscillator
* if we are in deep mode the output freq is 32.768khz
*/
mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT;
if (mode == RK3399_CLK_PLL_MODE_SLOW) {
dprintf("pll in slow mode, con4=%x\n", con4);
return (0);
} else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) {
dprintf("pll in deep slow, con4=%x\n", con4);
*freq = 32768;
return (0);
}
dprintf("con0: %x\n", con1);
dprintf("con1: %x\n", con2);
dprintf("con2: %x\n", con3);