Fixes for NVIDIA Tegra124 clocks:
- EMC clock have standard peripheral clock block. Use it. - Implement full frequency set method for PLLD2. This PLL is used as HDMI pixel clock so we must be able to set it to wide range of frequencies, within 5% tolerance allowed by HDMI specification. Due to this, full state space search (over m, n, p fields) is necessary. MFC after: 3 weeks
This commit is contained in:
Michal Meloun
parent
3b29466b94
commit
6f1eb3052e
@ -189,8 +189,6 @@ PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
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PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
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PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};
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PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};
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PLIST(mux_pllmcp_clkm) = {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
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"pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"};
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PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};
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PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};
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@ -240,7 +238,6 @@ static struct clk_mux_def tegra124_mux_clks[] = {
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/* Base peripheral clocks. */
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MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
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MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
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MUX(0, "emc_mux", mux_pllmcp_clkm, CLK_SOURCE_EMC, 29, 3),
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/* USB. */
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MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
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@ -126,6 +126,10 @@ PLIST(mux_m_c_p_a_c2_c3_clkm_c4) =
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PLIST(mux_m_c_p_clkm_mud_c2_c3) =
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{"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
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"pllM_UD", "pllC2_out0", "pllC3_out0"};
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PLIST(mux_m_c_p_clkm_mud_c2_c3_cud) =
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{"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
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"pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"};
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PLIST(mux_m_c2_c_c3_p_N_a) =
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{"pllM_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
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"pllP_out0", NULL, "pllA_out0"};
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@ -260,7 +264,7 @@ static struct pgate_def pgate_def[] = {
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GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
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GATE(UARTC, "uartc", "pc_uartc", H(23)),
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GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
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GATE(EMC, "emc", "emc_mux", H(25)),
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GATE(EMC, "emc", "pc_emc_2x", H(25)),
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GATE(USB2, "usb2", "clk_m", H(26)),
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GATE(USB3, "usb3", "clk_m", H(27)),
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GATE(VDE, "vde", "pc_vde", H(29)),
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@ -356,7 +360,7 @@ static struct pgate_def pgate_def[] = {
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/* GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)), */
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/* GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)), */
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GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
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/* GATE(VIM2_CLK, "vim2_clk", clk_m, X(11)), */
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GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)),
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/* GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)), */
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GATE(HDMI_AUDIO, "hdmi_audio", "pc_hdmi_audio", X(16)),
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GATE(CLK72MHZ, "clk72mhz", "pc_clk72mhz", X(17)),
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@ -373,17 +377,18 @@ static struct pgate_def pgate_def[] = {
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#define DCF_HAVE_ENA 0x0200 /* Block with enable bit */
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#define DCF_HAVE_DIV 0x0400 /* Block with divider */
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/* Mark block with additional bis / functionality. */
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/* Mark block with additional bits / functionality. */
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#define DCF_IS_MASK 0x00FF
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#define DCF_IS_UART 0x0001
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#define DCF_IS_VI 0x0002
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#define DCF_IS_HOST1X 0x0003
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#define DCF_IS_XUSB_SS 0x0004
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#define DCF_IS_EMC_DLL 0x0005
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#define FDS_IS_SATA 0x0006
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#define DCF_IS_SATA 0x0006
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#define DCF_IS_VIC 0x0007
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#define DCF_IS_AUDIO 0x0008
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#define DCF_IS_SOR0 0x0009
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#define DCF_IS_EMC 0x000A
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/* Basic pheripheral clock */
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#define PER_CLK(_id, cn, pl, r, diw, fiw, f) \
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@ -438,7 +443,7 @@ static struct periph_def periph_def[] = {
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CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
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CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
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CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
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/* EMC 8 */
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CLK_8_1(0, "pc_emc_2x", mux_m_c_p_clkm_mud_c2_c3_cud, CLK_SOURCE_EMC, DCF_IS_EMC),
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CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
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CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
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CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
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@ -476,7 +481,7 @@ static struct periph_def periph_def[] = {
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/* SYS */
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CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0),
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CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
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CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, FDS_IS_SATA),
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CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, DCF_IS_SATA),
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CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
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CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC,
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"pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
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@ -713,6 +713,7 @@ pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
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return (ERANGE);
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*fout = ((fin / m) * n) /p;
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return (0);
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}
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@ -771,7 +772,6 @@ pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
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{
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uint32_t m, n, p;
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p = 2;
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m = 1;
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n = (*fout * p * m + fin / 2)/ fin;
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@ -779,20 +779,89 @@ pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
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return (pll_set_std( sc, fin, fout, flags, m, n, p));
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}
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/*
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* PLLD2 is used as source for pixel clock for HDMI.
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* We must be able to set it frequency very flexibly and
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* precisely (within 5% tolerance limit allowed by HDMI specs).
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*
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* For this reason, it is necessary to search the full state space.
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* Fortunately, thanks to early cycle terminations, performance
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* is within acceptable limits.
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*/
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#define PLLD2_PFD_MIN 12000000 /* 12 MHz */
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#define PLLD2_PFD_MAX 38000000 /* 38 MHz */
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#define PLLD2_VCO_MIN 600000000 /* 600 MHz */
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#define PLLD2_VCO_MAX 1200000000 /* 1.2 GHz */
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static int
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plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
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{
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uint32_t m, n, p;
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uint32_t best_m, best_n, best_p;
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uint64_t vco, pfd;
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int64_t err, best_err;
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struct mnp_bits *mnp_bits;
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struct pdiv_table *tbl;
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int p_idx, rv;
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p = 2;
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m = 1;
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n = (*fout * p * m + fin / 2)/ fin;
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dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
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return (pll_set_std(sc, fin, fout, flags, m, n, p));
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mnp_bits = &sc->mnp_bits;
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tbl = sc->pdiv_table;
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best_err = INT64_MAX;
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for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
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p = tbl[p_idx].divider;
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/* Check constraints */
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vco = *fout * p;
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if (vco < PLLD2_VCO_MIN)
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continue;
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if (vco > PLLD2_VCO_MAX)
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break;
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for (m = 1; m < (1 << mnp_bits->m_width); m++) {
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n = (*fout * p * m + fin / 2) / fin;
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/* Check constraints */
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if (n == 0)
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continue;
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if (n >= (1 << mnp_bits->n_width))
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break;
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vco = (fin * n) / m;
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if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
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continue;
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pfd = fin / m;
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if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
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continue;
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/* Constraints passed, save best result */
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err = *fout - vco / p;
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if (err < 0)
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err = -err;
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if (err < best_err) {
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best_err = err;
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best_p = p;
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best_m = m;
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best_n = n;
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}
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if (err == 0)
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goto done;
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}
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}
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done:
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/*
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* HDMI specification allows 5% pixel clock tolerance,
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* we will by a slightly stricter
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*/
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if (best_err > ((*fout * 100) / 4))
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return (ERANGE);
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if (flags & CLK_SET_DRYRUN)
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return (0);
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rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
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/* XXXX Panic for rv == ERANGE ? */
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return (rv);
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}
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static int
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pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
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{
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@ -883,8 +952,8 @@ tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
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struct pll_sc *sc;
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sc = clknode_get_softc(clknode);
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dprintf("%s: Requested freq: %llu, input freq: %llu\n", __func__,
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*fout, fin);
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dprintf("%s: %s requested freq: %llu, input freq: %llu\n", __func__,
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clknode_get_name(clknode), *fout, fin);
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switch (sc->type) {
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case PLL_A:
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rv = plla_set_freq(sc, fin, fout, flags);
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