Fix a corner-case of interrupt handling which resulted in potentially
spurious (and fatal) interrupt errors. One user reported seeing this: Apr 22 18:04:24 ceres kernel: ar5416GetPendingInterrupts: fatal error, ISR_RAC 0x0 SYNC_CAUSE 0x2000 SYNC_CAUSE of 0x2000 is AR_INTR_SYNC_LOCAL_TIMEOUT which is a bus timeout; this shouldn't cause HAL_INT_FATAL to be set. After checking out ath9k, ath9k_ar9002_hw_get_isr() clears (*masked) before continuing, regardless of whether any bits in the ISR registers are set. So if AR_INTR_SYNC_CAUSE is set to something that isn't treated as fatal, and AR_ISR isn't read or is read and is 0, then (*masked) wouldn't be cleared. Thus any of the existing bits set that were passed in would be preserved in the output. The caller in if_ath - ath_intr() - wasn't setting the masked value to 0 before calling ath_hal_getisr(), so anything that was present in that uninitialised variable would be preserved in the case above of AR_ISR=0, AR_INTR_SYNC_CAUSE != 0; and if the HAL_INT_FATAL bit was set, a fatal condition would be interpreted and the chip was reset. This patch does the following: * ath_intr() - set masked to 0 before calling ath_hal_getisr(); * ar5416GetPendingInterrupts() - clear (*masked) before processing continues; so if the interrupt source is AR_INTR_SYNC_CAUSE and it isn't fatal, the hardware isn't reset via returning HAL_INT_FATAL. This doesn't fix any underlying errors which trigger AR_INTR_SYNC_LOCAL_TIMEOUT - which is a bus timeout of some sort - so that likely should be further investigated.
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@ -55,6 +55,8 @@ ar5416IsInterruptPending(struct ath_hal *ah)
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* values. The value returned is mapped to abstract the hw-specific bit
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* locations in the Interrupt Status Register.
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*
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* (*masked) is cleared on initial call.
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*
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* Returns: A hardware-abstracted bitmap of all non-masked-out
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* interrupts pending, as well as an unmasked value
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*/
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@ -73,10 +75,10 @@ ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
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isr = 0;
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sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
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sync_cause &= AR_INTR_SYNC_DEFAULT;
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if (isr == 0 && sync_cause == 0) {
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*masked = 0;
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*masked = 0;
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if (isr == 0 && sync_cause == 0)
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return AH_FALSE;
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}
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if (isr != 0) {
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struct ath_hal_5212 *ahp = AH5212(ah);
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@ -1265,7 +1265,7 @@ ath_intr(void *arg)
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struct ath_softc *sc = arg;
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struct ifnet *ifp = sc->sc_ifp;
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struct ath_hal *ah = sc->sc_ah;
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HAL_INT status;
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HAL_INT status = 0;
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if (sc->sc_invalid) {
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/*
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@ -1296,6 +1296,11 @@ ath_intr(void *arg)
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ath_hal_getisr(ah, &status); /* NB: clears ISR too */
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DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
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status &= sc->sc_imask; /* discard unasked for bits */
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/* Short-circuit un-handled interrupts */
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if (status == 0x0)
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return;
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if (status & HAL_INT_FATAL) {
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sc->sc_stats.ast_hardware++;
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ath_hal_intrset(ah, 0); /* disable intr's until reset */
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