Use defines for register offsets that do not change.
Submitted by: Hans Petter Selasky
This commit is contained in:
Andrew Thompson
parent
8060a8933e
commit
6f6932dc0b
@ -230,11 +230,11 @@ uss820dci_setup_rx(struct uss820dci_td *td)
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/* select the correct endpoint */
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->ep_reg, td->ep_index);
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USS820_EPINDEX, td->ep_index);
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/* read out FIFO status */
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rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_stat_reg);
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USS820_RXSTAT);
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/* get pointer to softc */
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sc = USS820_DCI_PC2SC(td->pc);
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@ -260,9 +260,9 @@ uss820dci_setup_rx(struct uss820dci_td *td)
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/* get the packet byte count */
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count = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_count_low_reg);
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USS820_RXCNTL);
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count |= (bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_count_high_reg) << 8);
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USS820_RXCNTH) << 8);
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count &= 0x3FF;
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/* verify data length */
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@ -278,11 +278,11 @@ uss820dci_setup_rx(struct uss820dci_td *td)
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}
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/* receive data */
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bus_space_read_multi_1(td->io_tag, td->io_hdl,
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td->rx_fifo_reg, (void *)&req, sizeof(req));
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USS820_RXDAT, (void *)&req, sizeof(req));
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/* read out FIFO status */
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rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_stat_reg);
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USS820_RXSTAT);
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if (rx_stat & (USS820_RXSTAT_EDOVW |
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USS820_RXSTAT_STOVW)) {
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@ -297,10 +297,10 @@ uss820dci_setup_rx(struct uss820dci_td *td)
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/* set RXFFRC bit */
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temp = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg);
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USS820_RXCON);
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temp |= USS820_RXCON_RXFFRC;
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg, temp);
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USS820_RXCON, temp);
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/* copy data into real buffer */
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usb2_copy_in(td->pc, 0, &req, sizeof(req));
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@ -321,10 +321,10 @@ setup_not_complete:
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/* set RXFFRC bit */
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temp = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg);
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USS820_RXCON);
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temp |= USS820_RXCON_RXFFRC;
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg, temp);
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USS820_RXCON, temp);
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/* FALLTHROUGH */
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@ -365,16 +365,16 @@ uss820dci_data_rx(struct uss820dci_td *td)
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got_short = 0;
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/* select the correct endpoint */
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bus_space_write_1(td->io_tag, td->io_hdl, td->ep_reg, td->ep_index);
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bus_space_write_1(td->io_tag, td->io_hdl, USS820_EPINDEX, td->ep_index);
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/* check if any of the FIFO banks have data */
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repeat:
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/* read out FIFO flag */
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rx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_flag_reg);
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USS820_RXFLG);
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/* read out FIFO status */
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rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_stat_reg);
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USS820_RXSTAT);
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DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n",
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rx_stat, rx_flag, td->remainder);
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@ -419,10 +419,10 @@ repeat:
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}
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/* get the packet byte count */
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count = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_count_low_reg);
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USS820_RXCNTL);
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count |= (bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_count_high_reg) << 8);
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USS820_RXCNTH) << 8);
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count &= 0x3FF;
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DPRINTFN(5, "count=0x%04x\n", count);
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@ -454,7 +454,7 @@ repeat:
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}
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/* receive data */
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bus_space_read_multi_1(td->io_tag, td->io_hdl,
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td->rx_fifo_reg, buf_res.buffer, buf_res.length);
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USS820_RXDAT, buf_res.buffer, buf_res.length);
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/* update counters */
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count -= buf_res.length;
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@ -464,10 +464,10 @@ repeat:
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/* set RXFFRC bit */
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rx_cntl = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg);
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USS820_RXCON);
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rx_cntl |= USS820_RXCON_RXFFRC;
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->rx_cntl_reg, rx_cntl);
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USS820_RXCON, rx_cntl);
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/* check if we are complete */
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if ((td->remainder == 0) || got_short) {
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@ -495,18 +495,18 @@ uss820dci_data_tx(struct uss820dci_td *td)
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/* select the correct endpoint */
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->ep_reg, td->ep_index);
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USS820_EPINDEX, td->ep_index);
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to = 2; /* don't loop forever! */
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repeat:
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/* read out TX FIFO flags */
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tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
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td->tx_flag_reg);
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USS820_TXFLG);
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/* read out RX FIFO status last */
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rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_stat_reg);
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USS820_RXSTAT);
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DPRINTFN(5, "rx_stat=0x%02x tx_flag=0x%02x rem=%u\n",
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rx_stat, tx_flag, td->remainder);
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@ -553,7 +553,7 @@ repeat:
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}
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/* transmit data */
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bus_space_write_multi_1(td->io_tag, td->io_hdl,
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td->tx_fifo_reg, buf_res.buffer, buf_res.length);
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USS820_TXDAT, buf_res.buffer, buf_res.length);
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/* update counters */
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count -= buf_res.length;
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@ -563,11 +563,11 @@ repeat:
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/* post-write high packet byte count first */
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->tx_count_high_reg, count_copy >> 8);
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USS820_TXCNTH, count_copy >> 8);
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/* post-write low packet byte count last */
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->tx_count_low_reg, count_copy);
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USS820_TXCNTL, count_copy);
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/*
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* Enable TX output, which must happen after that we have written
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@ -600,15 +600,15 @@ uss820dci_data_tx_sync(struct uss820dci_td *td)
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/* select the correct endpoint */
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bus_space_write_1(td->io_tag, td->io_hdl,
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td->ep_reg, td->ep_index);
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USS820_EPINDEX, td->ep_index);
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/* read out TX FIFO flag */
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tx_flag = bus_space_read_1(td->io_tag, td->io_hdl,
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td->tx_flag_reg);
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USS820_TXFLG);
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/* read out RX FIFO status last */
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rx_stat = bus_space_read_1(td->io_tag, td->io_hdl,
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td->rx_stat_reg);
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USS820_RXSTAT);
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DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder);
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@ -2269,20 +2269,6 @@ uss820dci_xfer_setup(struct usb2_setup_params *parm)
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td->io_tag = sc->sc_io_tag;
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td->io_hdl = sc->sc_io_hdl;
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td->max_packet_size = xfer->max_packet_size;
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td->rx_stat_reg = USS820_GET_REG(sc, USS820_RXSTAT);
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td->tx_stat_reg = USS820_GET_REG(sc, USS820_TXSTAT);
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td->rx_flag_reg = USS820_GET_REG(sc, USS820_RXFLG);
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td->tx_flag_reg = USS820_GET_REG(sc, USS820_TXFLG);
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td->rx_fifo_reg = USS820_GET_REG(sc, USS820_RXDAT);
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td->tx_fifo_reg = USS820_GET_REG(sc, USS820_TXDAT);
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td->rx_count_low_reg = USS820_GET_REG(sc, USS820_RXCNTL);
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td->rx_count_high_reg = USS820_GET_REG(sc, USS820_RXCNTH);
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td->tx_count_low_reg = USS820_GET_REG(sc, USS820_TXCNTL);
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td->tx_count_high_reg = USS820_GET_REG(sc, USS820_TXCNTH);
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td->rx_cntl_reg = USS820_GET_REG(sc, USS820_RXCON);
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td->tx_cntl_reg = USS820_GET_REG(sc, USS820_TXCON);
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td->pend_reg = USS820_GET_REG(sc, USS820_PEND);
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td->ep_reg = USS820_GET_REG(sc, USS820_EPINDEX);
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td->ep_index = ep_no;
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if (pf->support_multi_buffer &&
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(parm->methods != &uss820dci_device_ctrl_methods)) {
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@ -255,16 +255,11 @@
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#define USS820_UNK1 0x1f /* Unknown */
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#define USS820_UNK1_UNKNOWN 0xFF
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#define USS820_GET_REG(sc,reg) \
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((reg) << (sc)->sc_reg_shift)
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#define USS820_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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USS820_GET_REG(sc,reg))
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
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#define USS820_WRITE_1(sc, reg, data) \
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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USS820_GET_REG(sc,reg), data)
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
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struct uss820dci_td;
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@ -279,20 +274,6 @@ struct uss820dci_td {
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uint32_t offset;
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uint32_t remainder;
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uint16_t max_packet_size;
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uint8_t rx_stat_reg;
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uint8_t tx_stat_reg;
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uint8_t rx_flag_reg;
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uint8_t tx_flag_reg;
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uint8_t rx_fifo_reg;
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uint8_t tx_fifo_reg;
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uint8_t rx_count_low_reg;
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uint8_t rx_count_high_reg;
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uint8_t tx_count_low_reg;
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uint8_t tx_count_high_reg;
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uint8_t rx_cntl_reg;
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uint8_t tx_cntl_reg;
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uint8_t ep_reg;
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uint8_t pend_reg;
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uint8_t ep_index;
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uint8_t error:1;
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uint8_t alt_next:1;
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@ -356,7 +337,6 @@ struct uss820dci_softc {
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_dv_addr; /* device address */
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uint8_t sc_conf; /* root HUB config */
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uint8_t sc_reg_shift;
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uint8_t sc_hub_idata[1];
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