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Revert PCI RID changes.

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My PCI RID changes somehow got intermixed with my PCI ARI patch when I
committed it.  I may have accidentally applied a patch to a non-clean
working tree.  Revert everything while I figure out what went wrong.

Pointy hat to: rstone
This commit is contained in:
Ryan Stone 2014-04-01 15:06:03 +00:00
parent 956ed3830c
commit 7036ae46bf
20 changed files with 95 additions and 428 deletions
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4
sys/amd64/vmm/amd/amdv.c
View File

@ -242,14 +242,14 @@ amd_iommu_remove_mapping(void *domain, vm_paddr_t gpa, uint64_t len)
}
static void
amd_iommu_add_device(void *domain, uint16_t rid)
amd_iommu_add_device(void *domain, int bus, int slot, int func)
{
printf("amd_iommu_add_device: not implemented\n");
}
static void
amd_iommu_remove_device(void *domain, uint16_t rid)
amd_iommu_remove_device(void *domain, int bus, int slot, int func)
{
printf("amd_iommu_remove_device: not implemented\n");

28
sys/amd64/vmm/intel/vtd.c
View File

@ -99,8 +99,6 @@ struct vtdmap {
#define VTD_PTE_SUPERPAGE (1UL << 7)
#define VTD_PTE_ADDR_M (0x000FFFFFFFFFF000UL)
#define VTD_RID2IDX(rid) (((rid) & 0xff) * 2)
struct domain {
uint64_t *ptp; /* first level page table page */
int pt_levels; /* number of page table levels */
@ -362,24 +360,27 @@ vtd_disable(void)
}
static void
vtd_add_device(void *arg, uint16_t rid)
vtd_add_device(void *arg, int bus, int slot, int func)
{
int idx;
uint64_t *ctxp;
struct domain *dom = arg;
vm_paddr_t pt_paddr;
struct vtdmap *vtdmap;
uint8_t bus;
if (bus < 0 || bus > PCI_BUSMAX ||
slot < 0 || slot > PCI_SLOTMAX ||
func < 0 || func > PCI_FUNCMAX)
panic("vtd_add_device: invalid bsf %d/%d/%d", bus, slot, func);
vtdmap = vtdmaps[0];
bus = PCI_RID2BUS(rid);
ctxp = ctx_tables[bus];
pt_paddr = vtophys(dom->ptp);
idx = VTD_RID2IDX(rid);
idx = (slot << 3 | func) * 2;
if (ctxp[idx] & VTD_CTX_PRESENT) {
panic("vtd_add_device: device %x is already owned by "
"domain %d", rid,
panic("vtd_add_device: device %d/%d/%d is already owned by "
"domain %d", bus, slot, func,
(uint16_t)(ctxp[idx + 1] >> 8));
}
@ -403,16 +404,19 @@ vtd_add_device(void *arg, uint16_t rid)
}
static void
vtd_remove_device(void *arg, uint16_t rid)
vtd_remove_device(void *arg, int bus, int slot, int func)
{
int i, idx;
uint64_t *ctxp;
struct vtdmap *vtdmap;
uint8_t bus;
bus = PCI_RID2BUS(rid);
if (bus < 0 || bus > PCI_BUSMAX ||
slot < 0 || slot > PCI_SLOTMAX ||
func < 0 || func > PCI_FUNCMAX)
panic("vtd_add_device: invalid bsf %d/%d/%d", bus, slot, func);
ctxp = ctx_tables[bus];
idx = VTD_RID2IDX(rid);
idx = (slot << 3 | func) * 2;
/*
* Order is important. The 'present' bit is must be cleared first.

19
sys/amd64/vmm/io/iommu.c
View File

@ -109,19 +109,19 @@ IOMMU_REMOVE_MAPPING(void *domain, vm_paddr_t gpa, uint64_t len)
}
static __inline void
IOMMU_ADD_DEVICE(void *domain, uint16_t rid)
IOMMU_ADD_DEVICE(void *domain, int bus, int slot, int func)
{
if (ops != NULL && iommu_avail)
(*ops->add_device)(domain, rid);
(*ops->add_device)(domain, bus, slot, func);
}
static __inline void
IOMMU_REMOVE_DEVICE(void *domain, uint16_t rid)
IOMMU_REMOVE_DEVICE(void *domain, int bus, int slot, int func)
{
if (ops != NULL && iommu_avail)
(*ops->remove_device)(domain, rid);
(*ops->remove_device)(domain, bus, slot, func);
}
static __inline void
@ -196,8 +196,7 @@ iommu_init(void)
continue;
/* everything else belongs to the host domain */
iommu_add_device(host_domain,
pci_get_rid(dev));
iommu_add_device(host_domain, bus, slot, func);
}
}
}
@ -264,17 +263,17 @@ iommu_host_domain(void)
}
void
iommu_add_device(void *dom, uint16_t rid)
iommu_add_device(void *dom, int bus, int slot, int func)
{
IOMMU_ADD_DEVICE(dom, rid);
IOMMU_ADD_DEVICE(dom, bus, slot, func);
}
void
iommu_remove_device(void *dom, uint16_t rid)
iommu_remove_device(void *dom, int bus, int slot, int func)
{
IOMMU_REMOVE_DEVICE(dom, rid);
IOMMU_REMOVE_DEVICE(dom, bus, slot, func);
}
void

8
sys/amd64/vmm/io/iommu.h
View File

@ -39,8 +39,8 @@ typedef uint64_t (*iommu_create_mapping_t)(void *domain, vm_paddr_t gpa,
vm_paddr_t hpa, uint64_t len);
typedef uint64_t (*iommu_remove_mapping_t)(void *domain, vm_paddr_t gpa,
uint64_t len);
typedef void (*iommu_add_device_t)(void *domain, uint16_t rid);
typedef void (*iommu_remove_device_t)(void *dom, uint16_t rid);
typedef void (*iommu_add_device_t)(void *domain, int bus, int slot, int func);
typedef void (*iommu_remove_device_t)(void *dom, int bus, int slot, int func);
typedef void (*iommu_invalidate_tlb_t)(void *dom);
struct iommu_ops {
@ -69,7 +69,7 @@ void iommu_destroy_domain(void *dom);
void iommu_create_mapping(void *dom, vm_paddr_t gpa, vm_paddr_t hpa,
size_t len);
void iommu_remove_mapping(void *dom, vm_paddr_t gpa, size_t len);
void iommu_add_device(void *dom, uint16_t rid);
void iommu_remove_device(void *dom, uint16_t rid);
void iommu_add_device(void *dom, int bus, int slot, int func);
void iommu_remove_device(void *dom, int bus, int slot, int func);
void iommu_invalidate_tlb(void *domain);
#endif

4
sys/amd64/vmm/io/ppt.c
View File

@ -346,7 +346,7 @@ ppt_assign_device(struct vm *vm, int bus, int slot, int func)
return (EBUSY);
ppt->vm = vm;
iommu_add_device(vm_iommu_domain(vm), pci_get_rid(ppt->dev));
iommu_add_device(vm_iommu_domain(vm), bus, slot, func);
return (0);
}
return (ENOENT);
@ -367,7 +367,7 @@ ppt_unassign_device(struct vm *vm, int bus, int slot, int func)
ppt_unmap_mmio(vm, ppt);
ppt_teardown_msi(ppt);
ppt_teardown_msix(ppt);
iommu_remove_device(vm_iommu_domain(vm), pci_get_rid(ppt->dev));
iommu_remove_device(vm_iommu_domain(vm), bus, slot, func);
ppt->vm = NULL;
return (0);
}

1
sys/conf/files
View File

@ -1951,7 +1951,6 @@ dev/pci/pci_pci.c optional pci
dev/pci/pci_subr.c optional pci
dev/pci/pci_user.c optional pci
dev/pci/pcib_if.m standard
dev/pci/pcib_support.c standard
dev/pci/vga_pci.c optional pci
dev/pcn/if_pcn.c optional pcn pci
dev/pdq/if_fea.c optional fea eisa

59
sys/dev/pci/pci.c
View File

@ -124,8 +124,6 @@ static void pci_resume_msix(device_t dev);
static int pci_remap_intr_method(device_t bus, device_t dev,
u_int irq);
static uint16_t pci_get_rid_method(device_t dev, device_t child);
static device_method_t pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, pci_probe),
@ -184,7 +182,6 @@ static device_method_t pci_methods[] = {
DEVMETHOD(pci_release_msi, pci_release_msi_method),
DEVMETHOD(pci_msi_count, pci_msi_count_method),
DEVMETHOD(pci_msix_count, pci_msix_count_method),
DEVMETHOD(pci_get_rid, pci_get_rid_method),
DEVMETHOD_END
};
@ -354,11 +351,6 @@ SYSCTL_INT(_hw_pci, OID_AUTO, clear_buses, CTLFLAG_RDTUN, &pci_clear_buses, 0,
"Ignore firmware-assigned bus numbers.");
#endif
static int pci_enable_ari = 1;
TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari);
SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
0, "Enable support for PCIe Alternative RID Interpretation");
static int
pci_has_quirk(uint32_t devid, int quirk)
{
@ -3459,19 +3451,6 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
#endif
}
static struct pci_devinfo *
pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
int slot, int func, size_t dinfo_size)
{
struct pci_devinfo *dinfo;
dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size);
if (dinfo != NULL)
pci_add_child(dev, dinfo);
return (dinfo);
}
void
pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
{
@ -3481,24 +3460,6 @@ pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
int maxslots;
int s, f, pcifunchigh;
uint8_t hdrtype;
int first_func;
/*
* Try to detect a device at slot 0, function 0. If it exists, try to
* enable ARI. We must enable ARI before detecting the rest of the
* functions on this bus as ARI changes the set of slots and functions
* that are legal on this bus.
*/
dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0,
dinfo_size);
if (dinfo != NULL && pci_enable_ari)
PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
/*
* Start looking for new devices on slot 0 at function 1 because we
* just identified the device at slot 0, function 0.
*/
first_func = 1;
KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
("dinfo_size too small"));
@ -3511,13 +3472,14 @@ pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
continue;
if (hdrtype & PCIM_MFDEV)
pcifunchigh = PCIB_MAXFUNCS(pcib);
for (f = first_func; f <= pcifunchigh; f++)
pci_identify_function(pcib, dev, domain, busno, s, f,
pcifunchigh = PCI_FUNCMAX;
for (f = 0; f <= pcifunchigh; f++) {
dinfo = pci_read_device(pcib, domain, busno, s, f,
dinfo_size);
/* For slots after slot 0 we need to check for function 0. */
first_func = 0;
if (dinfo != NULL) {
pci_add_child(dev, dinfo);
}
}
}
#undef REG
}
@ -5093,10 +5055,3 @@ pci_restore_state(device_t dev)
dinfo = device_get_ivars(dev);
pci_cfg_restore(dev, dinfo);
}
static uint16_t
pci_get_rid_method(device_t dev, device_t child)
{
return (PCIB_GET_RID(device_get_parent(dev), child));
}

6
sys/dev/pci/pci_if.m
View File

@ -159,9 +159,3 @@ METHOD int msix_count {
device_t dev;
device_t child;
} DEFAULT null_msi_count;
METHOD uint16_t get_rid {
device_t dev;
device_t child;
};

156
sys/dev/pci/pci_pci.c
View File

@ -56,14 +56,6 @@ static int pcib_suspend(device_t dev);
static int pcib_resume(device_t dev);
static int pcib_power_for_sleep(device_t pcib, device_t dev,
int *pstate);
static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
u_int f, u_int reg, int width);
static void pcib_write_config(device_t dev, u_int b, u_int s,
u_int f, u_int reg, uint32_t val, int width);
static int pcib_ari_maxslots(device_t dev);
static int pcib_ari_maxfuncs(device_t dev);
static int pcib_try_enable_ari(device_t pcib, device_t dev);
static device_method_t pcib_methods[] = {
/* Device interface */
@ -91,8 +83,7 @@ static device_method_t pcib_methods[] = {
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
DEVMETHOD(pcib_maxslots, pcib_maxslots),
DEVMETHOD(pcib_read_config, pcib_read_config),
DEVMETHOD(pcib_write_config, pcib_write_config),
DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
@ -102,7 +93,6 @@ static device_method_t pcib_methods[] = {
DEVMETHOD(pcib_release_msix, pcib_release_msix),
DEVMETHOD(pcib_map_msi, pcib_map_msi),
DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
DEVMETHOD_END
};
@ -1811,104 +1801,28 @@ pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
}
#endif
/*
* If ARI is enabled on this downstream port, translate the function number
* to the non-ARI slot/function. The downstream port will convert it back in
* hardware. If ARI is not enabled slot and func are not modified.
*/
static __inline void
pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
{
struct pcib_softc *sc;
int ari_func;
sc = device_get_softc(pcib);
ari_func = *func;
if (sc->flags & PCIB_ENABLE_ARI) {
KASSERT(*slot == 0,
("Non-zero slot number with ARI enabled!"));
*slot = PCIE_ARI_SLOT(ari_func);
*func = PCIE_ARI_FUNC(ari_func);
}
}
static void
pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
{
uint32_t ctl2;
ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
ctl2 |= PCIEM_CTL2_ARI;
pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
sc->flags |= PCIB_ENABLE_ARI;
if (bootverbose)
device_printf(sc->dev, "Enable ARI\n");
}
/*
* PCIB interface.
*/
int
pcib_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
int
pcib_maxfuncs(device_t dev)
{
return (PCI_FUNCMAX);
}
static int
pcib_ari_maxslots(device_t dev)
{
struct pcib_softc *sc;
sc = device_get_softc(dev);
if (sc->flags & PCIB_ENABLE_ARI)
return (PCIE_ARI_SLOTMAX);
else
return (PCI_SLOTMAX);
}
static int
pcib_ari_maxfuncs(device_t dev)
{
struct pcib_softc *sc;
sc = device_get_softc(dev);
if (sc->flags & PCIB_ENABLE_ARI)
return (PCIE_ARI_FUNCMAX);
else
return (PCI_FUNCMAX);
return(PCI_SLOTMAX);
}
/*
* Since we are a child of a PCI bus, its parent must support the pcib interface.
*/
static uint32_t
uint32_t
pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
{
pcib_xlate_ari(dev, b, &s, &f);
return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
f, reg, width));
return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
}
static void
void
pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
{
pcib_xlate_ari(dev, b, &s, &f);
PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
reg, val, width);
PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
}
/*
@ -2020,61 +1934,3 @@ pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
bus = device_get_parent(pcib);
return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
}
/*
* Check that the downstream port (pcib) and the endpoint device (dev) both
* support ARI. If so, enable it and return 0, otherwise return an error.
*/
static int
pcib_try_enable_ari(device_t pcib, device_t dev)
{
struct pcib_softc *sc;
int error;
uint32_t cap2;
int ari_cap_off;
uint32_t ari_ver;
uint32_t pcie_pos;
sc = device_get_softc(pcib);
/*
* ARI is controlled in a register in the PCIe capability structure.
* If the downstream port does not have the PCIe capability structure
* then it does not support ARI.
*/
error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
if (error != 0)
return (ENODEV);
/* Check that the PCIe port advertises ARI support. */
cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
if (!(cap2 & PCIEM_CAP2_ARI))
return (ENODEV);
/*
* Check that the endpoint device advertises ARI support via the ARI
* extended capability structure.
*/
error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
if (error != 0)
return (ENODEV);
/*
* Finally, check that the endpoint device supports the same version
* of ARI that we do.
*/
ari_ver = pci_read_config(dev, ari_cap_off, 4);
if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
if (bootverbose)
device_printf(pcib,
"Unsupported version of ARI (%d) detected\n",
PCI_EXTCAP_VER(ari_ver));
return (ENXIO);
}
pcib_enable_ari(sc, pcie_pos);
return (0);
}

26
sys/dev/pci/pcib_if.m
View File

@ -46,14 +46,6 @@ METHOD int maxslots {
device_t dev;
};
#
#
# Return the number of functions on the attached PCI bus.
#
METHOD int maxfuncs {
device_t dev;
} default pcib_maxfuncs;
#
# Read configuration space on the PCI bus. The bus, slot and func
# arguments determine the device which is being read and the reg
@ -162,21 +154,3 @@ METHOD int power_for_sleep {
device_t dev;
int *pstate;
};
#
# Return the PCI Routing Identifier (RID) for the device.
#
METHOD uint16_t get_rid {
device_t pcib;
device_t dev;
};
#
# Enable Alternative RID Interpretation if both the downstream port (pcib)
# and the endpoint device (dev) both support it.
#
METHOD int try_enable_ari {
device_t pcib;
device_t dev;
};

8
sys/dev/pci/pcib_private.h
View File

@ -105,7 +105,6 @@ struct pcib_softc
#define PCIB_SUBTRACTIVE 0x1
#define PCIB_DISABLE_MSI 0x2
#define PCIB_DISABLE_MSIX 0x4
#define PCIB_ENABLE_ARI 0x8
uint16_t command; /* command register */
u_int domain; /* domain number */
u_int pribus; /* primary bus number */
@ -127,8 +126,6 @@ struct pcib_softc
uint8_t seclat; /* secondary bus latency timer */
};
#define PCIB_SUPPORTED_ARI_VER 1
typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
@ -162,14 +159,13 @@ int pcib_release_resource(device_t dev, device_t child, int type, int rid,
struct resource *r);
#endif
int pcib_maxslots(device_t dev);
int pcib_maxfuncs(device_t dev);
uint32_t pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width);
void pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width);
int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
int pcib_release_msix(device_t pcib, device_t dev, int irq);
int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
uint16_t pcib_get_rid(device_t pcib, device_t dev);
#endif

62
sys/dev/pci/pcib_support.c
View File

@ -1,62 +0,0 @@
/*
* Copyright (c) Sandvine Inc. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Support functions for the PCI:PCI bridge driver. This has to be in a
* separate file because kernel configurations end up referencing the functions
* here even when pci support is compiled out of the kernel.
*/
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <sys/systm.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
uint16_t
pcib_get_rid(device_t pcib, device_t dev)
{
uint8_t bus, slot, func;
bus = pci_get_bus(dev);
slot = pci_get_slot(dev);
func = pci_get_function(dev);
return (PCI_RID(bus, slot, func));
}

25
sys/dev/pci/pcireg.h
View File

@ -48,29 +48,6 @@
#define PCIE_REGMAX 4095 /* highest supported config register addr. */
#define PCI_MAXHDRTYPE 2
#define PCIE_ARI_SLOTMAX 0
#define PCIE_ARI_FUNCMAX 255
#define PCIE_ARI_SLOT(func) (((func) >> 3) & PCI_SLOTMAX)
#define PCIE_ARI_FUNC(func) ((func) & PCI_FUNCMAX)
#define PCI_RID_BUS_SHIFT 8
#define PCI_RID_SLOT_SHIFT 3
#define PCI_RID_FUNC_SHIFT 0
#define PCI_RID(bus, slot, func) \
((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
(((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \
(((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
#define PCI_ARI_RID(bus, func) \
((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \
(((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT))
#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX)
#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX)
#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX)
/* PCI config header registers for all devices */
#define PCIR_DEVVENDOR 0x00
@ -797,7 +774,6 @@
#define PCIEM_ROOT_STA_PME_STATUS 0x00010000
#define PCIEM_ROOT_STA_PME_PEND 0x00020000
#define PCIER_DEVICE_CAP2 0x24
#define PCIEM_CAP2_ARI 0x20
#define PCIER_DEVICE_CTL2 0x28
#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f
#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010
@ -918,4 +894,3 @@
/* Serial Number definitions */
#define PCIR_SERIAL_LOW 0x04
#define PCIR_SERIAL_HIGH 0x08

6
sys/dev/pci/pcivar.h
View File

@ -482,12 +482,6 @@ pci_msix_count(device_t dev)
return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
}
static __inline uint16_t
pci_get_rid(device_t dev)
{
return (PCI_GET_RID(device_get_parent(dev), dev));
}
device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
device_t pci_find_device(uint16_t, uint16_t);

24
sys/x86/iommu/busdma_dmar.c
View File

@ -93,7 +93,7 @@ dmar_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func)
* bounce mapping.
*/
static device_t
dmar_get_requester(device_t dev, uint16_t *rid)
dmar_get_requester(device_t dev, int *bus, int *slot, int *func)
{
devclass_t pci_class;
device_t pci, pcib, requester;
@ -102,7 +102,9 @@ dmar_get_requester(device_t dev, uint16_t *rid)
pci_class = devclass_find("pci");
requester = dev;
*rid = pci_get_rid(dev);
*bus = pci_get_bus(dev);
*slot = pci_get_slot(dev);
*func = pci_get_function(dev);
/*
* Walk the bridge hierarchy from the target device to the
@ -159,7 +161,8 @@ dmar_get_requester(device_t dev, uint16_t *rid)
* same page tables for taken and
* non-taken transactions.
*/
*rid = PCI_RID(pci_get_bus(dev), 0, 0);
*bus = pci_get_bus(dev);
*slot = *func = 0;
} else {
/*
* Neither the device nor the bridge
@ -168,7 +171,9 @@ dmar_get_requester(device_t dev, uint16_t *rid)
* will use the bridge's BSF as the
* requester ID.
*/
*rid = pci_get_rid(pcib);
*bus = pci_get_bus(pcib);
*slot = pci_get_slot(pcib);
*func = pci_get_function(pcib);
}
}
/*
@ -188,9 +193,9 @@ dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr)
device_t requester;
struct dmar_ctx *ctx;
bool disabled;
uint16_t rid;
int bus, slot, func;
requester = dmar_get_requester(dev, &rid);
requester = dmar_get_requester(dev, &bus, &slot, &func);
/*
* If the user requested the IOMMU disabled for the device, we
@ -199,10 +204,9 @@ dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev, bool rmrr)
* Instead provide the identity mapping for the device
* context.
*/
disabled = dmar_bus_dma_is_dev_disabled(pci_get_domain(requester),
pci_get_bus(requester), pci_get_slot(requester),
pci_get_function(requester));
ctx = dmar_get_ctx(dmar, requester, rid, disabled, rmrr);
disabled = dmar_bus_dma_is_dev_disabled(pci_get_domain(dev), bus,
slot, func);
ctx = dmar_get_ctx(dmar, requester, bus, slot, func, disabled, rmrr);
if (ctx == NULL)
return (NULL);
if (disabled) {

40
sys/x86/iommu/intel_ctx.c
View File

@ -63,7 +63,6 @@ __FBSDID("$FreeBSD$");
#include <x86/iommu/intel_reg.h>
#include <x86/iommu/busdma_dmar.h>
#include <x86/iommu/intel_dmar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context");
@ -106,14 +105,14 @@ dmar_map_ctx_entry(struct dmar_ctx *ctx, struct sf_buf **sfp)
{
dmar_ctx_entry_t *ctxp;
ctxp = dmar_map_pgtbl(ctx->dmar->ctx_obj, 1 + PCI_RID2BUS(ctx->rid),
ctxp = dmar_map_pgtbl(ctx->dmar->ctx_obj, 1 + ctx->bus,
DMAR_PGF_NOALLOC | DMAR_PGF_WAITOK, sfp);
ctxp += ctx->rid & 0xff;
ctxp += ((ctx->slot & 0x1f) << 3) + (ctx->func & 0x7);
return (ctxp);
}
static void
ctx_tag_init(struct dmar_ctx *ctx, device_t dev)
ctx_tag_init(struct dmar_ctx *ctx)
{
bus_addr_t maxaddr;
@ -127,7 +126,6 @@ ctx_tag_init(struct dmar_ctx *ctx, device_t dev)
ctx->ctx_tag.common.nsegments = BUS_SPACE_UNRESTRICTED;
ctx->ctx_tag.common.maxsegsz = maxaddr;
ctx->ctx_tag.ctx = ctx;
ctx->ctx_tag.owner = dev;
/* XXXKIB initialize tag further */
}
@ -140,10 +138,7 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp)
unit = ctx->dmar;
KASSERT(ctxp->ctx1 == 0 && ctxp->ctx2 == 0,
("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx",
unit->unit, pci_get_bus(ctx->ctx_tag.owner),
pci_get_slot(ctx->ctx_tag.owner),
pci_get_function(ctx->ctx_tag.owner),
ctxp->ctx1,
unit->unit, ctx->bus, ctx->slot, ctx->func, ctxp->ctx1,
ctxp->ctx2));
ctxp->ctx2 = DMAR_CTX2_DID(ctx->domain);
ctxp->ctx2 |= ctx->awlvl;
@ -232,7 +227,7 @@ ctx_init_rmrr(struct dmar_ctx *ctx, device_t dev)
}
static struct dmar_ctx *
dmar_get_ctx_alloc(struct dmar_unit *dmar, uint16_t rid)
dmar_get_ctx_alloc(struct dmar_unit *dmar, int bus, int slot, int func)
{
struct dmar_ctx *ctx;
@ -242,7 +237,9 @@ dmar_get_ctx_alloc(struct dmar_unit *dmar, uint16_t rid)
TASK_INIT(&ctx->unload_task, 0, dmar_ctx_unload_task, ctx);
mtx_init(&ctx->lock, "dmarctx", NULL, MTX_DEF);
ctx->dmar = dmar;
ctx->rid = rid;
ctx->bus = bus;
ctx->slot = slot;
ctx->func = func;
return (ctx);
}
@ -265,22 +262,19 @@ dmar_ctx_dtr(struct dmar_ctx *ctx, bool gas_inited, bool pgtbl_inited)
}
struct dmar_ctx *
dmar_get_ctx(struct dmar_unit *dmar, device_t dev, uint16_t rid, bool id_mapped,
bool rmrr_init)
dmar_get_ctx(struct dmar_unit *dmar, device_t dev, int bus, int slot, int func,
bool id_mapped, bool rmrr_init)
{
struct dmar_ctx *ctx, *ctx1;
dmar_ctx_entry_t *ctxp;
struct sf_buf *sf;
int bus, slot, func, error, mgaw;
int error, mgaw;
bool enable;
bus = pci_get_bus(dev);
slot = pci_get_slot(dev);
func = pci_get_function(dev);
enable = false;
TD_PREP_PINNED_ASSERT;
DMAR_LOCK(dmar);
ctx = dmar_find_ctx_locked(dmar, rid);
ctx = dmar_find_ctx_locked(dmar, bus, slot, func);
error = 0;
if (ctx == NULL) {
/*
@ -289,7 +283,7 @@ dmar_get_ctx(struct dmar_unit *dmar, device_t dev, uint16_t rid, bool id_mapped,
*/
DMAR_UNLOCK(dmar);
dmar_ensure_ctx_page(dmar, bus);
ctx1 = dmar_get_ctx_alloc(dmar, rid);
ctx1 = dmar_get_ctx_alloc(dmar, bus, slot, func);
if (id_mapped) {
/*
@ -357,7 +351,7 @@ dmar_get_ctx(struct dmar_unit *dmar, device_t dev, uint16_t rid, bool id_mapped,
* Recheck the contexts, other thread might have
* already allocated needed one.
*/
ctx = dmar_find_ctx_locked(dmar, rid);
ctx = dmar_find_ctx_locked(dmar, bus, slot, func);
if (ctx == NULL) {
ctx = ctx1;
ctx->ctx_tag.owner = dev;
@ -369,7 +363,7 @@ dmar_get_ctx(struct dmar_unit *dmar, device_t dev, uint16_t rid, bool id_mapped,
TD_PINNED_ASSERT;
return (NULL);
}
ctx_tag_init(ctx, dev);
ctx_tag_init(ctx);
/*
* This is the first activated context for the
@ -530,14 +524,14 @@ dmar_free_ctx(struct dmar_ctx *ctx)
}
struct dmar_ctx *
dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid)
dmar_find_ctx_locked(struct dmar_unit *dmar, int bus, int slot, int func)
{
struct dmar_ctx *ctx;
DMAR_ASSERT_LOCKED(dmar);
LIST_FOREACH(ctx, &dmar->contexts, link) {
if (ctx->rid == rid)
if (ctx->bus == bus && ctx->slot == slot && ctx->func == func)
return (ctx);
}
return (NULL);

11
sys/x86/iommu/intel_dmar.h
View File

@ -74,7 +74,9 @@ RB_PROTOTYPE(dmar_gas_entries_tree, dmar_map_entry, rb_entry,
#define DMAR_MAP_ENTRY_TM 0x8000 /* Transient */
struct dmar_ctx {
uint16_t rid; /* pci RID */
int bus; /* pci bus/slot/func */
int slot;
int func;
int domain; /* DID */
int mgaw; /* Real max address width */
int agaw; /* Adjusted guest address width */
@ -267,11 +269,12 @@ void ctx_free_pgtbl(struct dmar_ctx *ctx);
struct dmar_ctx *dmar_instantiate_ctx(struct dmar_unit *dmar, device_t dev,
bool rmrr);
struct dmar_ctx *dmar_get_ctx(struct dmar_unit *dmar, device_t dev,
uint16_t rid, bool id_mapped, bool rmrr_init);
struct dmar_ctx *dmar_get_ctx(struct dmar_unit *dmar, device_t dev,
int bus, int slot, int func, bool id_mapped, bool rmrr_init);
void dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx);
void dmar_free_ctx(struct dmar_ctx *ctx);
struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, uint16_t rid);
struct dmar_ctx *dmar_find_ctx_locked(struct dmar_unit *dmar, int bus,
int slot, int func);
void dmar_ctx_unload_entry(struct dmar_map_entry *entry, bool free);
void dmar_ctx_unload(struct dmar_ctx *ctx,
struct dmar_map_entries_tailq *entries, bool cansleep);

10
sys/x86/iommu/intel_drv.c
View File

@ -1005,9 +1005,7 @@ dmar_print_ctx(struct dmar_ctx *ctx, bool show_mappings)
db_printf(
" @%p pci%d:%d:%d dom %d mgaw %d agaw %d pglvl %d end %jx\n"
" refs %d flags %x pgobj %p map_ents %u loads %lu unloads %lu\n",
ctx, pci_get_bus(ctx->ctx_tag.owner),
pci_get_slot(ctx->ctx_tag.owner),
pci_get_function(ctx->ctx_tag.owner), ctx->domain, ctx->mgaw,
ctx, ctx->bus, ctx->slot, ctx->func, ctx->domain, ctx->mgaw,
ctx->agaw, ctx->pglvl, (uintmax_t)ctx->end, ctx->refs,
ctx->flags, ctx->pgtbl_obj, ctx->entries_cnt, ctx->loads,
ctx->unloads);
@ -1080,10 +1078,8 @@ DB_FUNC(dmar_ctx, db_dmar_print_ctx, db_show_table, CS_OWN, NULL)
for (i = 0; i < dmar_devcnt; i++) {
unit = device_get_softc(dmar_devs[i]);
LIST_FOREACH(ctx, &unit->contexts, link) {
if (domain == unit->segment &&
bus == pci_get_bus(ctx->ctx_tag.owner) &&
device == pci_get_slot(ctx->ctx_tag.owner) &&
function == pci_get_function(ctx->ctx_tag.owner)) {
if (domain == unit->segment && bus == ctx->bus &&
device == ctx->slot && function == ctx->func) {
dmar_print_ctx(ctx, show_mappings);
goto out;
}

19
sys/x86/iommu/intel_fault.c
View File

@ -45,8 +45,6 @@ __FBSDID("$FreeBSD$");
#include <contrib/dev/acpica/include/acpi.h>
#include <contrib/dev/acpica/include/accommon.h>
#include <dev/acpica/acpivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <vm/vm.h>
#include <vm/vm_extern.h>
#include <vm/vm_kern.h>
@ -205,28 +203,19 @@ dmar_fault_task(void *arg, int pending __unused)
DMAR_FAULT_UNLOCK(unit);
sid = DMAR_FRCD2_SID(fault_rec[1]);
bus = (sid >> 8) & 0xf;
slot = (sid >> 3) & 0x1f;
func = sid & 0x7;
printf("DMAR%d: ", unit->unit);
DMAR_LOCK(unit);
ctx = dmar_find_ctx_locked(unit, sid);
ctx = dmar_find_ctx_locked(unit, bus, slot, func);
if (ctx == NULL) {
printf("<unknown dev>:");
/*
* Note that the slot and function will not be correct
* if ARI is in use, but without a ctx entry we have
* no way of knowing whether ARI is in use or not.
*/
bus = PCI_RID2BUS(sid);
slot = PCI_RID2SLOT(sid);
func = PCI_RID2FUNC(sid);
} else {
ctx->flags |= DMAR_CTX_FAULTED;
ctx->last_fault_rec[0] = fault_rec[0];
ctx->last_fault_rec[1] = fault_rec[1];
device_print_prettyname(ctx->ctx_tag.owner);
bus = pci_get_bus(ctx->ctx_tag.owner);
slot = pci_get_slot(ctx->ctx_tag.owner);
func = pci_get_function(ctx->ctx_tag.owner);
}
DMAR_UNLOCK(unit);
printf(

7
sys/x86/iommu/intel_utils.c
View File

@ -47,7 +47,6 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/taskqueue.h>
#include <sys/tree.h>
#include <dev/pci/pcivar.h>
#include <vm/vm.h>
#include <vm/vm_extern.h>
#include <vm/vm_kern.h>
@ -130,10 +129,8 @@ ctx_set_agaw(struct dmar_ctx *ctx, int mgaw)
}
device_printf(ctx->dmar->dev,
"context request mgaw %d for pci%d:%d:%d:%d, "
"no agaw found, sagaw %x\n", mgaw, ctx->dmar->segment,
pci_get_bus(ctx->ctx_tag.owner),
pci_get_slot(ctx->ctx_tag.owner),
pci_get_function(ctx->ctx_tag.owner), sagaw);
"no agaw found, sagaw %x\n", mgaw, ctx->dmar->segment, ctx->bus,
ctx->slot, ctx->func, sagaw);
return (EINVAL);
}