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Add Qlogic 10Gb Ethernet Driver for Qlogic 8100 Series CNA Adapter

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Driver version (v2.0.0)

Submitted by: David C Somayajulu (davidcs@freebsd.org) QLogic Corporation
Approved by: George Neville-Neil (gnn@freebsd.org)
This commit is contained in:
David C Somayajulu 2013-06-25 17:50:22 +00:00
parent d58802817b
commit 711bcba0bb
21 changed files with 9360 additions and 0 deletions
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3
share/man/man4/Makefile
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@ -371,6 +371,7 @@ MAN= aac.4 \
pts.4 \
pty.4 \
puc.4 \
${_qlxge.4} \
${_qlxgb.4} \
${_qlxgbe.4} \
ral.4 \
@ -793,10 +794,12 @@ _bhyve.4= bhyve.4
_if_ntb.4= if_ntb.4
_ntb.4= ntb.4
_ntb_hw.4= ntb_hw.4
_qlxge.4= qlxge.4
_qlxgb.4= qlxgb.4
_qlxgbe.4= qlxgbe.4
_sfxge.4= sfxge.4
MLINKS+=qlxge.4 if_qlxge.4
MLINKS+=qlxgb.4 if_qlxgb.4
MLINKS+=qlxgbe.4 if_qlxgbe.4
MLINKS+=sfxge.4 if_sfxge.4

91
share/man/man4/qlxge.4 Normal file
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@ -0,0 +1,91 @@
.\"-
.\" Copyright (c) 2013-2014 Qlogic Corporation
.\" All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. Redistributions in binary form must reproduce the above copyright
.\" notice, this list of conditions and the following disclaimer in the
.\" documentation and/or other materials provided with the distribution.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd June 21, 2013
.Dt QLXGE 4
.Os
.Sh NAME
.Nm qlxge
.Nd "QLogic 8100 Series 10 Gigabit Ethernet Adapter Driver"
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device qlxge"
.Ed
.Pp
To load the driver as a
module at boot time, place the following line in
.Xr loader.conf 5 :
.Bd -literal -offset indent
if_qlxge_load="YES"
.Ed
.Sh DESCRIPTION
The
.Nm
driver supports IPv4 checksum offload,
TCP and UDP checksum offload for both IPv4 and IPv6,
Large Segment Offload for both IPv4 and IPv6,
Jumbo frames, VLAN Tag, and
Receive Side scaling.
For further hardware information, see
.Pa http://www.qlogic.com/ .
.Sh HARDWARE
The
.Nm
driver supports 10 Gigabit Ethernet & CNA Adapter based on the following
chipsets:
.Pp
.Bl -bullet -compact
.It
QLogic 8100 series
.El
.Sh SUPPORT
For support questions please contact your QLogic approved reseller or
QLogic Technical Support at
.Pa http://support.qlogic.com ,
or by E-mail at
.Aq support@qlogic.com .
.Sh SEE ALSO
.Xr altq 4 ,
.Xr arp 4 ,
.Xr netintro 4 ,
.Xr ng_ether 4 ,
.Xr ifconfig 8
.Sh HISTORY
The
.Nm
device driver first appeared in
.Fx 10.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was written by
.An David C Somayajulu
at QLogic Corporation.

6
sys/conf/files.amd64
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@ -227,6 +227,12 @@ dev/nvme/nvme_test.c optional nvme
dev/nvram/nvram.c optional nvram isa
dev/random/ivy.c optional random rdrand_rng
dev/random/nehemiah.c optional random padlock_rng
dev/qlxge/qls_dbg.c optional qlxge pci
dev/qlxge/qls_dump.c optional qlxge pci
dev/qlxge/qls_hw.c optional qlxge pci
dev/qlxge/qls_ioctl.c optional qlxge pci
dev/qlxge/qls_isr.c optional qlxge pci
dev/qlxge/qls_os.c optional qlxge pci
dev/qlxgb/qla_dbg.c optional qlxgb pci
dev/qlxgb/qla_hw.c optional qlxgb pci
dev/qlxgb/qla_ioctl.c optional qlxgb pci

97
sys/dev/qlxge/README.txt Normal file
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@ -0,0 +1,97 @@
#$FreeBSD$
README File
QLogic 8100 series Dual Port
10 Gigabit Ethernet & CNA Adapter Driver for FreeBSD 9.x/10.x
QLogic Corporation.
All rights reserved.
Table of Contents
1. Package Contents
2. OS Support
3. Supported Features
4. Using the Driver
4.1 Installing the driver
4.2 Removing the driver
5. Driver Parameters
6. Additional Notes
7. Contacting Support
1. Package Contents
* Documentation
- README (this document) version:1.0
- Release Notes Version:1.0
* Driver (if_qlxge.ko)
- FreeBSD 9.x/10.x
* Firmware: pre-flashed on QLogic adapter;
2. OS Support
The Qlogic 10Gigabit Ethernet/CNA driver is compatible with the
following OS platforms:
* FreeBSD 9.x/10.x (64-bit) [Intel EM64T, AMD64]
3. Supported Features
10Gigabit Ethernet NIC/CNA driver supports following features
* Large Segment Offload over TCP IPV4
* Large Segment Offload over TCP IPV6
* Receive Side scaling
* TCP over IPv4 checksum offload
* UDP over IPv4 checksum offload
* IPV4 checksum offload
* TCP over IPv6 checksum offload
* UDP over IPv6 checksum offload
* Jumbo frames
* VLAN Tag
4. Using the driver
4.1 Installing the driver
- copy the driver file (if_qlxge.ko) into some directory (say qla_driver)
- cd <to qla_driver>
- kldload -v ./if_qlxge.ko
4.2 Removing the driver
- kldunload if_qlxge
5. Parameters to set prior to installing the driver
- Add the following lines to /etc/sysctl.conf and reboot the machine prior
to installing the driver
net.inet.tcp.recvbuf_max=262144
net.inet.tcp.recvbuf_inc=16384
kern.ipc.nmbclusters=1000000
kern.ipc.maxsockbuf=2097152
net.inet.tcp.recvspace=131072
net.inet.tcp.sendbuf_max=262144
net.inet.tcp.sendspace=65536
- If you do not want to reboot the system please run the following commands
login or su to root
sysctl net.inet.tcp.recvbuf_max=262144
sysctl net.inet.tcp.recvbuf_inc=16384
sysctl kern.ipc.nmbclusters=1000000
sysctl kern.ipc.maxsockbuf=2097152
sysctl net.inet.tcp.recvspace=131072
sysctl net.inet.tcp.sendbuf_max=262144
sysctl net.inet.tcp.sendspace=65536
7. Contacting Support
Please feel free to contact your QLogic approved reseller or QLogic
Technical Support at any phase of integration for assistance. QLogic
Technical Support can be reached by the following methods:
Web: http://support.qlogic.com
E-mail: support@qlogic.com
(c) Copyright 2013-14. All rights reserved worldwide. QLogic, the QLogic
logo, and the Powered by QLogic logo are registered trademarks of
QLogic Corporation. All other brand and product names are trademarks
or registered trademarks of their respective owners.

307
sys/dev/qlxge/qls_dbg.c Normal file
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@ -0,0 +1,307 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File : qls_dbg.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "qls_os.h"
#include "qls_hw.h"
#include "qls_def.h"
#include "qls_inline.h"
#include "qls_ver.h"
#include "qls_glbl.h"
#include "qls_dbg.h"
uint32_t qls_dbg_level = 0 ;
/*
* Name: qls_dump_buf32
* Function: dumps a buffer as 32 bit words
*/
void
qls_dump_buf32(qla_host_t *ha, const char *msg, void *dbuf32, uint32_t len32)
{
device_t dev;
uint32_t i = 0;
uint32_t *buf;
dev = ha->pci_dev;
buf = dbuf32;
device_printf(dev, "%s: %s dump start\n", __func__, msg);
while (len32 >= 4) {
device_printf(dev,"0x%08x:\t0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
i, buf[0], buf[1], buf[2], buf[3]);
i += 4 * 4;
len32 -= 4;
buf += 4;
}
switch (len32) {
case 1:
device_printf(dev,"0x%08x: 0x%08x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: 0x%08x 0x%08x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: 0x%08x 0x%08x 0x%08x\n",
i, buf[0], buf[1], buf[2]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
return;
}
/*
* Name: qls_dump_buf16
* Function: dumps a buffer as 16 bit words
*/
void
qls_dump_buf16(qla_host_t *ha, const char *msg, void *dbuf16, uint32_t len16)
{
device_t dev;
uint32_t i = 0;
uint16_t *buf;
dev = ha->pci_dev;
buf = dbuf16;
device_printf(dev, "%s: %s dump start\n", __func__, msg);
while (len16 >= 8) {
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x 0x%04x"
" 0x%04x 0x%04x 0x%04x 0x%04x\n", i, buf[0],
buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
i += 16;
len16 -= 8;
buf += 8;
}
switch (len16) {
case 1:
device_printf(dev,"0x%08x: 0x%04x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: 0x%04x 0x%04x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x\n",
i, buf[0], buf[1], buf[2]);
break;
case 4:
device_printf(dev,"0x%08x: 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3]);
break;
case 5:
device_printf(dev,"0x%08x:"
" 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4]);
break;
case 6:
device_printf(dev,"0x%08x:"
" 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
break;
case 7:
device_printf(dev,"0x%04x: 0x%04x 0x%04x 0x%04x 0x%04x"
" 0x%04x 0x%04x 0x%04x\n", i, buf[0], buf[1],
buf[2], buf[3], buf[4], buf[5], buf[6]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
return;
}
/*
* Name: qls_dump_buf8
* Function: dumps a buffer as bytes
*/
void
qls_dump_buf8(qla_host_t *ha, const char *msg, void *dbuf, uint32_t len)
{
device_t dev;
uint32_t i = 0;
uint8_t *buf;
dev = ha->pci_dev;
buf = dbuf;
device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
while (len >= 16) {
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7],
buf[8], buf[9], buf[10], buf[11],
buf[12], buf[13], buf[14], buf[15]);
i += 16;
len -= 16;
buf += 16;
}
switch (len) {
case 1:
device_printf(dev,"0x%08x: %02x\n", i, buf[0]);
break;
case 2:
device_printf(dev,"0x%08x: %02x %02x\n", i, buf[0], buf[1]);
break;
case 3:
device_printf(dev,"0x%08x: %02x %02x %02x\n",
i, buf[0], buf[1], buf[2]);
break;
case 4:
device_printf(dev,"0x%08x: %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3]);
break;
case 5:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4]);
break;
case 6:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
break;
case 7:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
break;
case 8:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7]);
break;
case 9:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8]);
break;
case 10:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9]);
break;
case 11:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10]);
break;
case 12:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11]);
break;
case 13:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12]);
break;
case 14:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
buf[13]);
break;
case 15:
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x\n", i,
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
buf[13], buf[14]);
break;
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
return;
}
void
qls_dump_cq(qla_host_t *ha)
{
qls_dump_buf32(ha, "cq_icb", ha->rx_ring[0].cq_icb_vaddr,
(sizeof (q81_cq_icb_t) >> 2));
device_printf(ha->pci_dev, "%s: lbq_addr_tbl_paddr %p\n", __func__,
(void *)ha->rx_ring[0].lbq_addr_tbl_paddr);
qls_dump_buf32(ha, "lbq_addr_tbl", ha->rx_ring[0].lbq_addr_tbl_vaddr,
(PAGE_SIZE >> 2));
device_printf(ha->pci_dev, "%s: lbq_paddr %p\n", __func__,
(void *)ha->rx_ring[0].lbq_paddr);
qls_dump_buf32(ha, "lbq", ha->rx_ring[0].lbq_vaddr,
(QLA_LBQ_SIZE >> 2));
device_printf(ha->pci_dev, "%s: sbq_addr_tbl_paddr %p\n", __func__,
(void *)ha->rx_ring[0].sbq_addr_tbl_paddr);
qls_dump_buf32(ha, "sbq_addr_tbl", ha->rx_ring[0].sbq_addr_tbl_vaddr,
(PAGE_SIZE >> 2));
device_printf(ha->pci_dev, "%s: sbq_paddr %p\n", __func__,
(void *)ha->rx_ring[0].sbq_paddr);
qls_dump_buf32(ha, "sbq", ha->rx_ring[0].sbq_vaddr,
(QLA_SBQ_SIZE >> 2) );
device_printf(ha->pci_dev, "%s: lb_paddr %p\n", __func__,
(void *)ha->rx_ring[0].lb_paddr);
return;
}

94
sys/dev/qlxge/qls_dbg.h Normal file
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@ -0,0 +1,94 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File : qls_dbg.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QL_DBG_H_
#define _QL_DBG_H_
extern uint32_t qls_dbg_level;
extern void qls_dump_buf8(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len);
extern void qls_dump_buf16(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len16);
extern void qls_dump_buf32(qla_host_t *ha, const char *str, void *dbuf,
uint32_t len32);
extern void qls_dump_cq(qla_host_t *ha);
#ifdef QL_DBG
#define QL_DPRINT1(x) if (qls_dbg_level & 0x0001) device_printf x
#define QL_DPRINT2(x) if (qls_dbg_level & 0x0002) device_printf x
#define QL_DPRINT4(x) if (qls_dbg_level & 0x0004) device_printf x
#define QL_DPRINT8(x) if (qls_dbg_level & 0x0008) device_printf x
#define QL_DPRINT10(x) if (qls_dbg_level & 0x0010) device_printf x
#define QL_DPRINT20(x) if (qls_dbg_level & 0x0020) device_printf x
#define QL_DPRINT40(x) if (qls_dbg_level & 0x0040) device_printf x
#define QL_DPRINT80(x) if (qls_dbg_level & 0x0080) device_printf x
#define QL_DUMP_BUFFER8(h, s, b, n) if (qls_dbg_level & 0x08000000)\
qls_dump_buf8(h, s, b, n)
#define QL_DUMP_BUFFER16(h, s, b, n) if (qls_dbg_level & 0x08000000)\
qls_dump_buf16(h, s, b, n)
#define QL_DUMP_BUFFER32(h, s, b, n) if (qls_dbg_level & 0x08000000)\
qls_dump_buf32(h, s, b, n)
#define QL_ASSERT(ha, x, y) if (!x && !ha->err_inject) panic y
#define QL_DUMP_CQ(ha) if (qls_dbg_level & 0x08000000) qls_dump_cq(ha)
#else
#define QL_DPRINT1(x)
#define QL_DPRINT2(x)
#define QL_DPRINT4(x)
#define QL_DPRINT8(x)
#define QL_DPRINT10(x)
#define QL_DPRINT20(x)
#define QL_DPRINT40(x)
#define QL_DPRINT80(x)
#define QL_DUMP_BUFFER8(h, s, b, n)
#define QL_DUMP_BUFFER16(h, s, b, n)
#define QL_DUMP_BUFFER32(h, s, b, n)
#define QL_ASSERT(ha, x, y)
#define QL_DUMP_CQ(ha)
#endif
#endif /* #ifndef _QL_DBG_H_ */

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sys/dev/qlxge/qls_def.h Normal file
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@ -0,0 +1,377 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_def.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QLS_DEF_H_
#define _QLS_DEF_H_
/*
* structure encapsulating a DMA buffer
*/
struct qla_dma {
bus_size_t alignment;
uint32_t size;
void *dma_b;
bus_addr_t dma_addr;
bus_dmamap_t dma_map;
bus_dma_tag_t dma_tag;
};
typedef struct qla_dma qla_dma_t;
/*
* structure encapsulating interrupt vectors
*/
struct qla_ivec {
uint32_t cq_idx;
void *ha;
struct resource *irq;
void *handle;
int irq_rid;
};
typedef struct qla_ivec qla_ivec_t;
/*
* Transmit Related Definitions
*/
#define MAX_TX_RINGS 1
#define NUM_TX_DESCRIPTORS 1024
#define QLA_MAX_SEGMENTS 64 /* maximum # of segs in a sg list */
#define QLA_OAL_BLK_SIZE (sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
#define QLA_TX_OALB_TOTAL_SIZE (NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
#define QLA_TX_PRIVATE_BSIZE ((QLA_TX_OALB_TOTAL_SIZE + \
PAGE_SIZE + \
(PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
#define QLA_MAX_MTU 9000
#define QLA_STD_FRAME_SIZE 1514
#define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
#define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
struct qla_tx_buf {
struct mbuf *m_head;
bus_dmamap_t map;
/* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
bus_addr_t oal_paddr;
void *oal_vaddr;
};
typedef struct qla_tx_buf qla_tx_buf_t;
struct qla_tx_ring {
volatile struct {
uint32_t wq_dma:1,
privb_dma:1;
} flags;
qla_dma_t privb_dma;
qla_dma_t wq_dma;
qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
uint64_t count;
struct resource *wq_db_addr;
uint32_t wq_db_offset;
q81_tx_cmd_t *wq_vaddr;
bus_addr_t wq_paddr;
void *wq_icb_vaddr;
bus_addr_t wq_icb_paddr;
uint32_t *txr_cons_vaddr;
bus_addr_t txr_cons_paddr;
volatile uint32_t txr_free; /* # of free entries in tx ring */
volatile uint32_t txr_next; /* # next available tx ring entry */
volatile uint32_t txr_done;
uint64_t tx_frames;
uint64_t tx_tso_frames;
uint64_t tx_vlan_frames;
};
typedef struct qla_tx_ring qla_tx_ring_t;
/*
* Receive Related Definitions
*/
#define MAX_RX_RINGS MAX_TX_RINGS
#define NUM_RX_DESCRIPTORS 1024
#define NUM_CQ_ENTRIES NUM_RX_DESCRIPTORS
#define QLA_LGB_SIZE (12 * 1024)
#define QLA_NUM_LGB_ENTRIES 32
#define QLA_LBQ_SIZE (QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
#define QLA_LGBQ_AND_TABLE_SIZE \
((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
/* Please note that Small Buffer size is determined by max mtu size */
#define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS
#define QLA_SBQ_SIZE (QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
#define QLA_SMBQ_AND_TABLE_SIZE \
((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
struct qla_rx_buf {
struct mbuf *m_head;
bus_dmamap_t map;
bus_addr_t paddr;
void *next;
};
typedef struct qla_rx_buf qla_rx_buf_t;
struct qla_rx_ring {
volatile struct {
uint32_t cq_dma:1,
lbq_dma:1,
sbq_dma:1,
lb_dma:1;
} flags;
qla_dma_t cq_dma;
qla_dma_t lbq_dma;
qla_dma_t sbq_dma;
qla_dma_t lb_dma;
struct lro_ctrl lro;
qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
qla_rx_buf_t *rxb_free;
uint32_t rx_free;
uint32_t rx_next;
uint32_t cq_db_offset;
void *cq_icb_vaddr;
bus_addr_t cq_icb_paddr;
uint32_t *cqi_vaddr;
bus_addr_t cqi_paddr;
void *cq_base_vaddr;
bus_addr_t cq_base_paddr;
uint32_t cq_next; /* next cq entry to process */
void *lbq_addr_tbl_vaddr;
bus_addr_t lbq_addr_tbl_paddr;
void *lbq_vaddr;
bus_addr_t lbq_paddr;
uint32_t lbq_next; /* next entry in LBQ to process */
uint32_t lbq_free;/* # of entries in LBQ to arm */
uint32_t lbq_in; /* next entry in LBQ to arm */
void *lb_vaddr;
bus_addr_t lb_paddr;
void *sbq_addr_tbl_vaddr;
bus_addr_t sbq_addr_tbl_paddr;
void *sbq_vaddr;
bus_addr_t sbq_paddr;
uint32_t sbq_next; /* next entry in SBQ to process */
uint32_t sbq_free;/* # of entries in SBQ to arm */
uint32_t sbq_in; /* next entry in SBQ to arm */
uint64_t rx_int;
uint64_t rss_int;
};
typedef struct qla_rx_ring qla_rx_ring_t;
#define QLA_WATCHDOG_CALLOUT_TICKS 1
/*
* Multicast Definitions
*/
typedef struct _qla_mcast {
uint16_t rsrvd;
uint8_t addr[6];
} __packed qla_mcast_t;
/*
* Misc. definitions
*/
#define QLA_PAGE_SIZE 4096
/*
* Adapter structure contains the hardware independant information of the
* pci function.
*/
struct qla_host {
volatile struct {
volatile uint32_t
mpi_dma :1,
rss_dma :1,
intr_enable :1,
qla_callout_init :1,
qla_watchdog_active :1,
qla_watchdog_exit :1,
qla_watchdog_pause :1,
lro_init :1,
parent_tag :1,
lock_init :1;
} flags;
volatile uint32_t hw_init;
volatile uint32_t qla_watchdog_exited;
volatile uint32_t qla_watchdog_paused;
volatile uint32_t qla_initiate_recovery;
device_t pci_dev;
uint8_t pci_func;
uint16_t watchdog_ticks;
uint8_t resvd;
/* ioctl related */
struct cdev *ioctl_dev;
/* register mapping */
struct resource *pci_reg;
int reg_rid;
struct resource *pci_reg1;
int reg_rid1;
int msix_count;
qla_ivec_t irq_vec[MAX_RX_RINGS];
/* parent dma tag */
bus_dma_tag_t parent_tag;
/* interface to o.s */
struct ifnet *ifp;
struct ifmedia media;
uint16_t max_frame_size;
uint16_t rsrvd0;
uint32_t msize;
int if_flags;
/* hardware access lock */
struct mtx hw_lock;
volatile uint32_t hw_lock_held;
uint32_t vm_pgsize;
/* transmit related */
uint32_t num_tx_rings;
qla_tx_ring_t tx_ring[MAX_TX_RINGS];
bus_dma_tag_t tx_tag;
struct task tx_task;
struct taskqueue *tx_tq;
struct callout tx_callout;
struct mtx tx_lock;
/* receive related */
uint32_t num_rx_rings;
qla_rx_ring_t rx_ring[MAX_RX_RINGS];
bus_dma_tag_t rx_tag;
/* stats */
uint32_t err_m_getcl;
uint32_t err_m_getjcl;
uint32_t err_tx_dmamap_create;
uint32_t err_tx_dmamap_load;
uint32_t err_tx_defrag;
/* mac address related */
uint8_t mac_rcv_mode;
uint8_t mac_addr[ETHER_ADDR_LEN];
uint32_t nmcast;
qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
/* Link Related */
uint8_t link_up;
uint32_t link_status;
uint32_t link_down_info;
uint32_t link_hw_info;
uint32_t link_dcbx_counters;
uint32_t link_change_counters;
/* Flash Related */
q81_flash_t flash;
/* debug stuff */
volatile const char *qla_lock;
volatile const char *qla_unlock;
/* Error Recovery Related */
uint32_t err_inject;
struct task err_task;
struct taskqueue *err_tq;
/* Chip related */
uint32_t rev_id;
/* mailbox completions */
uint32_t aen[Q81_NUM_AEN_REGISTERS];
uint32_t mbox[Q81_NUM_MBX_REGISTERS];
volatile uint32_t mbx_done;
/* mpi dump related */
qla_dma_t mpi_dma;
qla_dma_t rss_dma;
};
typedef struct qla_host qla_host_t;
/* note that align has to be a power of 2 */
#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
#define QL_MIN(x, y) ((x < y) ? x : y)
#define QL_RUNNING(ifp) \
((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
IFF_DRV_RUNNING)
/* Return 0, if identical, else 1 */
#define QL_MAC_CMP(mac1, mac2) \
((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
#endif /* #ifndef _QLS_DEF_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_dump.h
*/
#ifndef _QLS_DUMP_H_
#define _QLS_DUMP_H_
#define Q81_MPID_COOKIE 0x5555aaaa
typedef struct qls_mpid_glbl_hdr
{
uint32_t cookie;
uint8_t id[16];
uint32_t time_lo;
uint32_t time_hi;
uint32_t img_size;
uint32_t hdr_size;
uint8_t info[220];
} qls_mpid_glbl_hdr_t;
typedef struct qls_mpid_seg_hdr
{
uint32_t cookie;
uint32_t seg_num;
uint32_t seg_size;
uint32_t extra;
uint8_t desc[16];
} qls_mpid_seg_hdr_t;
enum
{
Q81_MPI_CORE_REGS_ADDR = 0x00030000,
Q81_MPI_CORE_REGS_CNT = 127,
Q81_MPI_CORE_SH_REGS_CNT = 16,
Q81_TEST_REGS_ADDR = 0x00001000,
Q81_TEST_REGS_CNT = 23,
Q81_RMII_REGS_ADDR = 0x00001040,
Q81_RMII_REGS_CNT = 64,
Q81_FCMAC1_REGS_ADDR = 0x00001080,
Q81_FCMAC2_REGS_ADDR = 0x000010c0,
Q81_FCMAC_REGS_CNT = 64,
Q81_FC1_MBX_REGS_ADDR = 0x00001100,
Q81_FC2_MBX_REGS_ADDR = 0x00001240,
Q81_FC_MBX_REGS_CNT = 64,
Q81_IDE_REGS_ADDR = 0x00001140,
Q81_IDE_REGS_CNT = 64,
Q81_NIC1_MBX_REGS_ADDR = 0x00001180,
Q81_NIC2_MBX_REGS_ADDR = 0x00001280,
Q81_NIC_MBX_REGS_CNT = 64,
Q81_SMBUS_REGS_ADDR = 0x00001200,
Q81_SMBUS_REGS_CNT = 64,
Q81_I2C_REGS_ADDR = 0x00001fc0,
Q81_I2C_REGS_CNT = 64,
Q81_MEMC_REGS_ADDR = 0x00003000,
Q81_MEMC_REGS_CNT = 256,
Q81_PBUS_REGS_ADDR = 0x00007c00,
Q81_PBUS_REGS_CNT = 256,
Q81_MDE_REGS_ADDR = 0x00010000,
Q81_MDE_REGS_CNT = 6,
Q81_CODE_RAM_ADDR = 0x00020000,
Q81_CODE_RAM_CNT = 0x2000,
Q81_MEMC_RAM_ADDR = 0x00100000,
Q81_MEMC_RAM_CNT = 0x2000,
Q81_XGMAC_REGISTER_END = 0x740,
};
#define Q81_PROBE_DATA_LENGTH_WORDS ((64*2) + 1)
#define Q81_NUMBER_OF_PROBES 34
#define Q81_PROBE_SIZE \
(Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES)
#define Q81_NUMBER_ROUTING_REG_ENTRIES 48
#define Q81_WORDS_PER_ROUTING_REG_ENTRY 4
#define Q81_ROUT_REG_SIZE \
(Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY)
#define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\
(4096 * 1) + (4 * 2) +\
(8 * 2) + (16 * 1) +\
(4 * 1) + (4 * 4) + (4 * 1))
#define Q81_WORDS_PER_MAC_PROT_ENTRY 2
#define Q81_MAC_REG_SIZE \
(Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY)
#define Q81_MAX_SEMAPHORE_FUNCTIONS 5
#define Q81_WQC_WORD_SIZE 6
#define Q81_NUMBER_OF_WQCS 128
#define Q81_WQ_SIZE (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS)
#define Q81_CQC_WORD_SIZE 13
#define Q81_NUMBER_OF_CQCS 128
#define Q81_CQ_SIZE (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS)
struct qls_mpi_coredump {
qls_mpid_glbl_hdr_t mpi_global_header;
qls_mpid_seg_hdr_t core_regs_seg_hdr;
uint32_t mpi_core_regs[Q81_MPI_CORE_REGS_CNT];
uint32_t mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT];
qls_mpid_seg_hdr_t test_logic_regs_seg_hdr;
uint32_t test_logic_regs[Q81_TEST_REGS_CNT];
qls_mpid_seg_hdr_t rmii_regs_seg_hdr;
uint32_t rmii_regs[Q81_RMII_REGS_CNT];
qls_mpid_seg_hdr_t fcmac1_regs_seg_hdr;
uint32_t fcmac1_regs[Q81_FCMAC_REGS_CNT];
qls_mpid_seg_hdr_t fcmac2_regs_seg_hdr;
uint32_t fcmac2_regs[Q81_FCMAC_REGS_CNT];
qls_mpid_seg_hdr_t fc1_mbx_regs_seg_hdr;
uint32_t fc1_mbx_regs[Q81_FC_MBX_REGS_CNT];
qls_mpid_seg_hdr_t ide_regs_seg_hdr;
uint32_t ide_regs[Q81_IDE_REGS_CNT];
qls_mpid_seg_hdr_t nic1_mbx_regs_seg_hdr;
uint32_t nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT];
qls_mpid_seg_hdr_t smbus_regs_seg_hdr;
uint32_t smbus_regs[Q81_SMBUS_REGS_CNT];
qls_mpid_seg_hdr_t fc2_mbx_regs_seg_hdr;
uint32_t fc2_mbx_regs[Q81_FC_MBX_REGS_CNT];
qls_mpid_seg_hdr_t nic2_mbx_regs_seg_hdr;
uint32_t nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT];
qls_mpid_seg_hdr_t i2c_regs_seg_hdr;
uint32_t i2c_regs[Q81_I2C_REGS_CNT];
qls_mpid_seg_hdr_t memc_regs_seg_hdr;
uint32_t memc_regs[Q81_MEMC_REGS_CNT];
qls_mpid_seg_hdr_t pbus_regs_seg_hdr;
uint32_t pbus_regs[Q81_PBUS_REGS_CNT];
qls_mpid_seg_hdr_t mde_regs_seg_hdr;
uint32_t mde_regs[Q81_MDE_REGS_CNT];
qls_mpid_seg_hdr_t xaui1_an_hdr;
uint32_t serdes1_xaui_an[14];
qls_mpid_seg_hdr_t xaui1_hss_pcs_hdr;
uint32_t serdes1_xaui_hss_pcs[33];
qls_mpid_seg_hdr_t xfi1_an_hdr;
uint32_t serdes1_xfi_an[14];
qls_mpid_seg_hdr_t xfi1_train_hdr;
uint32_t serdes1_xfi_train[12];
qls_mpid_seg_hdr_t xfi1_hss_pcs_hdr;
uint32_t serdes1_xfi_hss_pcs[15];
qls_mpid_seg_hdr_t xfi1_hss_tx_hdr;
uint32_t serdes1_xfi_hss_tx[32];
qls_mpid_seg_hdr_t xfi1_hss_rx_hdr;
uint32_t serdes1_xfi_hss_rx[32];
qls_mpid_seg_hdr_t xfi1_hss_pll_hdr;
uint32_t serdes1_xfi_hss_pll[32];
qls_mpid_seg_hdr_t xaui2_an_hdr;
uint32_t serdes2_xaui_an[14];
qls_mpid_seg_hdr_t xaui2_hss_pcs_hdr;
uint32_t serdes2_xaui_hss_pcs[33];
qls_mpid_seg_hdr_t xfi2_an_hdr;
uint32_t serdes2_xfi_an[14];
qls_mpid_seg_hdr_t xfi2_train_hdr;
uint32_t serdes2_xfi_train[12];
qls_mpid_seg_hdr_t xfi2_hss_pcs_hdr;
uint32_t serdes2_xfi_hss_pcs[15];
qls_mpid_seg_hdr_t xfi2_hss_tx_hdr;
uint32_t serdes2_xfi_hss_tx[32];
qls_mpid_seg_hdr_t xfi2_hss_rx_hdr;
uint32_t serdes2_xfi_hss_rx[32];
qls_mpid_seg_hdr_t xfi2_hss_pll_hdr;
uint32_t serdes2_xfi_hss_pll[32];
qls_mpid_seg_hdr_t nic1_regs_seg_hdr;
uint32_t nic1_regs[64];
qls_mpid_seg_hdr_t nic2_regs_seg_hdr;
uint32_t nic2_regs[64];
qls_mpid_seg_hdr_t intr_states_seg_hdr;
uint32_t intr_states[MAX_RX_RINGS];
qls_mpid_seg_hdr_t xgmac1_seg_hdr;
uint32_t xgmac1[Q81_XGMAC_REGISTER_END];
qls_mpid_seg_hdr_t xgmac2_seg_hdr;
uint32_t xgmac2[Q81_XGMAC_REGISTER_END];
qls_mpid_seg_hdr_t probe_dump_seg_hdr;
uint32_t probe_dump[Q81_PROBE_SIZE];
qls_mpid_seg_hdr_t routing_reg_seg_hdr;
uint32_t routing_regs[Q81_ROUT_REG_SIZE];
qls_mpid_seg_hdr_t mac_prot_reg_seg_hdr;
uint32_t mac_prot_regs[Q81_MAC_REG_SIZE];
qls_mpid_seg_hdr_t sem_regs_seg_hdr;
uint32_t sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS];
qls_mpid_seg_hdr_t ets_seg_hdr;
uint32_t ets[8+2];
qls_mpid_seg_hdr_t wqc1_seg_hdr;
uint32_t wqc1[Q81_WQ_SIZE];
qls_mpid_seg_hdr_t cqc1_seg_hdr;
uint32_t cqc1[Q81_CQ_SIZE];
qls_mpid_seg_hdr_t wqc2_seg_hdr;
uint32_t wqc2[Q81_WQ_SIZE];
qls_mpid_seg_hdr_t cqc2_seg_hdr;
uint32_t cqc2[Q81_CQ_SIZE];
qls_mpid_seg_hdr_t code_ram_seg_hdr;
uint32_t code_ram[Q81_CODE_RAM_CNT];
qls_mpid_seg_hdr_t memc_ram_seg_hdr;
uint32_t memc_ram[Q81_MEMC_RAM_CNT];
};
typedef struct qls_mpi_coredump qls_mpi_coredump_t;
#define Q81_BAD_DATA 0xDEADBEEF
#endif /* #ifndef _QLS_DUMP_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_glbl.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
* Content: Contains prototypes of the exported functions from each file.
*/
#ifndef _QLS_GLBL_H_
#define _QLS_GLBL_H_
/*
* from qls_isr.c
*/
extern void qls_isr(void *arg);
/*
* from qls_os.c
*/
extern int qls_alloc_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf);
extern void qls_free_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf);
extern int qls_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp);
/*
* from qls_hw.c
*/
extern int qls_init_host_fw(qla_host_t *ha);
extern int qls_get_msix_count(qla_host_t *ha);
extern void qls_hw_add_sysctls(qla_host_t *ha);
extern void qls_free_dma(qla_host_t *ha);
extern int qls_alloc_dma(qla_host_t *ha);
extern int qls_set_promisc(qla_host_t *ha);
extern void qls_reset_promisc(qla_host_t *ha);
extern int qls_set_allmulti(qla_host_t *ha);
extern void qls_reset_allmulti(qla_host_t *ha);
extern int qls_hw_tx_done(qla_host_t *ha, uint32_t txr_idx);
extern int qls_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx);
extern void qls_del_hw_if(qla_host_t *ha);
extern int qls_init_hw_if(qla_host_t *ha);
extern void qls_hw_set_multi(qla_host_t *ha, uint8_t *mta, uint32_t mcnt,
uint32_t add_multi);
extern void qls_update_link_state(qla_host_t *ha);
extern int qls_init_hw(qla_host_t *ha);
extern int qls_rd_flash32(qla_host_t *ha, uint32_t addr, uint32_t *data);
extern int qls_rd_nic_params(qla_host_t *ha);
extern int qls_mbx_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data);
extern int qls_mbx_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data);
extern int qls_mpi_risc_rd_reg(qla_host_t *ha, uint32_t reg, uint32_t *data);
extern int qls_mpi_risc_wr_reg(qla_host_t *ha, uint32_t reg, uint32_t data);
extern int qls_mbx_dump_risc_ram(qla_host_t *ha, void *buf, uint32_t r_addr,
uint32_t r_size);
extern int qls_mpi_reset(qla_host_t *ha);
/*
* from qls_ioctl.c
*/
extern int qls_make_cdev(qla_host_t *ha);
extern void qls_del_cdev(qla_host_t *ha);
extern int qls_mpi_core_dump(qla_host_t *ha);
#endif /* #ifndef_QLS_GLBL_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_inline.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QLS_INLINE_H_
#define _QLS_INLINE_H_
static __inline int
qls_get_ifq_snd_maxlen(qla_host_t *ha)
{
return((NUM_TX_DESCRIPTORS - 1));
}
static __inline uint32_t
qls_get_optics(qla_host_t *ha)
{
uint32_t link_speed = 0;
if (ha->link_up) {
switch ((ha->link_hw_info & 0xF0)) {
case (0x01 << 4):
case (0x02 << 4):
case (0x03 << 4):
link_speed = (IFM_10G_LR | IFM_10G_SR);
break;
case (0x04 << 4):
case (0x05 << 4):
case (0x06 << 4):
link_speed = IFM_10G_TWINAX;
break;
case (0x07 << 4):
case (0x08 << 4):
case (0x09 << 4):
case (0x0A << 4):
case (0x0B << 4):
link_speed = IFM_1000_SX;
break;
}
}
return(link_speed);
}
static __inline uint8_t *
qls_get_mac_addr(qla_host_t *ha)
{
return (ha->mac_addr);
}
static __inline int
qls_lock(qla_host_t *ha, const char *str, uint32_t no_delay)
{
int ret = -1;
while (1) {
mtx_lock(&ha->hw_lock);
if (!ha->hw_lock_held) {
ha->hw_lock_held = 1;
ha->qla_lock = str;
ret = 0;
mtx_unlock(&ha->hw_lock);
break;
}
mtx_unlock(&ha->hw_lock);
if (no_delay)
break;
else
qls_mdelay(__func__, 1);
}
return (ret);
}
static __inline void
qls_unlock(qla_host_t *ha, const char *str)
{
mtx_lock(&ha->hw_lock);
ha->hw_lock_held = 0;
ha->qla_unlock = str;
mtx_unlock(&ha->hw_lock);
}
#endif /* #ifndef _QLS_INLINE_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File: qls_ioctl.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "qls_os.h"
#include "qls_hw.h"
#include "qls_def.h"
#include "qls_inline.h"
#include "qls_glbl.h"
#include "qls_ioctl.h"
#include "qls_dump.h"
extern qls_mpi_coredump_t ql_mpi_coredump;
static int qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct thread *td);
static struct cdevsw qla_cdevsw = {
.d_version = D_VERSION,
.d_ioctl = qls_eioctl,
.d_name = "qlxge",
};
int
qls_make_cdev(qla_host_t *ha)
{
ha->ioctl_dev = make_dev(&qla_cdevsw,
ha->ifp->if_dunit,
UID_ROOT,
GID_WHEEL,
0600,
"%s",
if_name(ha->ifp));
if (ha->ioctl_dev == NULL)
return (-1);
ha->ioctl_dev->si_drv1 = ha;
return (0);
}
void
qls_del_cdev(qla_host_t *ha)
{
if (ha->ioctl_dev != NULL)
destroy_dev(ha->ioctl_dev);
return;
}
static int
qls_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct thread *td)
{
qla_host_t *ha;
int rval = 0;
device_t pci_dev;
qls_mpi_dump_t *mpi_dump;
if ((ha = (qla_host_t *)dev->si_drv1) == NULL)
return ENXIO;
pci_dev= ha->pci_dev;
switch(cmd) {
case QLA_MPI_DUMP:
mpi_dump = (qls_mpi_dump_t *)data;
if (mpi_dump->size == 0) {
mpi_dump->size = sizeof (qls_mpi_coredump_t);
} else {
if (mpi_dump->size < sizeof (qls_mpi_coredump_t))
rval = EINVAL;
else {
qls_mpi_core_dump(ha);
rval = copyout( &ql_mpi_coredump,
mpi_dump->dbuf,
mpi_dump->size);
if (rval) {
device_printf(ha->pci_dev,
"%s: mpidump failed[%d]\n",
__func__, rval);
}
}
}
break;
default:
break;
}
return rval;
}

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_ioctl.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QLS_IOCTL_H_
#define _QLS_IOCTL_H_
#include <sys/ioccom.h>
struct qls_mpi_dump {
uint32_t size;
void *dbuf;
};
typedef struct qls_mpi_dump qls_mpi_dump_t;
/*
* Get MPI Dump
*/
#define QLA_MPI_DUMP _IOWR('q', 1, qls_mpi_dump_t)
#endif /* #ifndef _QLS_IOCTL_H_ */

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* File: qls_isr.c
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "qls_os.h"
#include "qls_hw.h"
#include "qls_def.h"
#include "qls_inline.h"
#include "qls_ver.h"
#include "qls_glbl.h"
#include "qls_dbg.h"
static void
qls_tx_comp(qla_host_t *ha, uint32_t txr_idx, q81_tx_mac_comp_t *tx_comp)
{
qla_tx_buf_t *txb;
uint32_t tx_idx = tx_comp->tid_lo;
if (tx_idx >= NUM_TX_DESCRIPTORS) {
ha->qla_initiate_recovery = 1;
return;
}
txb = &ha->tx_ring[txr_idx].tx_buf[tx_idx];
if (txb->m_head) {
ha->ifp->if_opackets++;
bus_dmamap_sync(ha->tx_tag, txb->map,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(ha->tx_tag, txb->map);
m_freem(txb->m_head);
txb->m_head = NULL;
}
ha->tx_ring[txr_idx].txr_done++;
if (ha->tx_ring[txr_idx].txr_done == NUM_TX_DESCRIPTORS)
ha->tx_ring[txr_idx].txr_done = 0;
}
static void
qls_replenish_rx(qla_host_t *ha, uint32_t r_idx)
{
qla_rx_buf_t *rxb;
qla_rx_ring_t *rxr;
int count;
volatile q81_bq_addr_e_t *sbq_e;
rxr = &ha->rx_ring[r_idx];
count = rxr->rx_free;
sbq_e = rxr->sbq_vaddr;
while (count--) {
rxb = &rxr->rx_buf[rxr->sbq_next];
if (rxb->m_head == NULL) {
if (qls_get_mbuf(ha, rxb, NULL) != 0) {
device_printf(ha->pci_dev,
"%s: qls_get_mbuf [0,%d,%d] failed\n",
__func__, rxr->sbq_next, r_idx);
rxb->m_head = NULL;
break;
}
}
if (rxb->m_head != NULL) {
sbq_e[rxr->sbq_next].addr_lo = (uint32_t)rxb->paddr;
sbq_e[rxr->sbq_next].addr_hi =
(uint32_t)(rxb->paddr >> 32);
rxr->sbq_next++;
if (rxr->sbq_next == NUM_RX_DESCRIPTORS)
rxr->sbq_next = 0;
rxr->sbq_free++;
rxr->rx_free--;
}
if (rxr->sbq_free == 16) {
rxr->sbq_in += 16;
rxr->sbq_in = rxr->sbq_in & (NUM_RX_DESCRIPTORS - 1);
rxr->sbq_free = 0;
Q81_WR_SBQ_PROD_IDX(r_idx, (rxr->sbq_in));
}
}
}
static int
qls_rx_comp(qla_host_t *ha, uint32_t rxr_idx, uint32_t cq_idx, q81_rx_t *cq_e)
{
qla_rx_buf_t *rxb;
qla_rx_ring_t *rxr;
device_t dev = ha->pci_dev;
struct mbuf *mp = NULL;
struct ifnet *ifp = ha->ifp;
struct lro_ctrl *lro;
struct ether_vlan_header *eh;
rxr = &ha->rx_ring[rxr_idx];
lro = &rxr->lro;
rxb = &rxr->rx_buf[rxr->rx_next];
if (!(cq_e->flags1 & Q81_RX_FLAGS1_DS)) {
device_printf(dev, "%s: DS bit not set \n", __func__);
return -1;
}
if (rxb->paddr != cq_e->b_paddr) {
device_printf(dev,
"%s: (rxb->paddr != cq_e->b_paddr)[%p, %p] \n",
__func__, (void *)rxb->paddr, (void *)cq_e->b_paddr);
Q81_SET_CQ_INVALID(cq_idx);
ha->qla_initiate_recovery = 1;
return(-1);
}
rxr->rx_int++;
if ((cq_e->flags1 & Q81_RX_FLAGS1_ERR_MASK) == 0) {
mp = rxb->m_head;
rxb->m_head = NULL;
if (mp == NULL) {
device_printf(dev, "%s: mp == NULL\n", __func__);
} else {
mp->m_flags |= M_PKTHDR;
mp->m_pkthdr.len = cq_e->length;
mp->m_pkthdr.rcvif = ifp;
mp->m_len = cq_e->length;
eh = mtod(mp, struct ether_vlan_header *);
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
uint32_t *data = (uint32_t *)eh;
mp->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
mp->m_flags |= M_VLANTAG;
*(data + 3) = *(data + 2);
*(data + 2) = *(data + 1);
*(data + 1) = *data;
m_adj(mp, ETHER_VLAN_ENCAP_LEN);
}
if ((cq_e->flags1 & Q81_RX_FLAGS1_RSS_MATCH_MASK)) {
rxr->rss_int++;
mp->m_pkthdr.flowid = cq_e->rss;
mp->m_flags |= M_FLOWID;
}
if (cq_e->flags0 & (Q81_RX_FLAGS0_TE |
Q81_RX_FLAGS0_NU | Q81_RX_FLAGS0_IE)) {
mp->m_pkthdr.csum_flags = 0;
} else {
mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED |
CSUM_IP_VALID | CSUM_DATA_VALID |
CSUM_PSEUDO_HDR;
mp->m_pkthdr.csum_data = 0xFFFF;
}
ifp->if_ipackets++;
if (lro->lro_cnt && (tcp_lro_rx(lro, mp, 0) == 0)) {
/* LRO packet has been successfuly queued */
} else {
(*ifp->if_input)(ifp, mp);
}
}
} else {
device_printf(dev, "%s: err [0%08x]\n", __func__, cq_e->flags1);
}
rxr->rx_free++;
rxr->rx_next++;
if (rxr->rx_next == NUM_RX_DESCRIPTORS)
rxr->rx_next = 0;
if ((rxr->rx_free + rxr->sbq_free) >= 16)
qls_replenish_rx(ha, rxr_idx);
return 0;
}
static void
qls_cq_isr(qla_host_t *ha, uint32_t cq_idx)
{
q81_cq_e_t *cq_e, *cq_b;
uint32_t i, cq_comp_idx;
int ret = 0, tx_comp_done = 0;
struct lro_ctrl *lro;
struct lro_entry *queued;
cq_b = ha->rx_ring[cq_idx].cq_base_vaddr;
lro = &ha->rx_ring[cq_idx].lro;
cq_comp_idx = *(ha->rx_ring[cq_idx].cqi_vaddr);
i = ha->rx_ring[cq_idx].cq_next;
while (i != cq_comp_idx) {
cq_e = &cq_b[i];
switch (cq_e->opcode) {
case Q81_IOCB_TX_MAC:
case Q81_IOCB_TX_TSO:
qls_tx_comp(ha, cq_idx, (q81_tx_mac_comp_t *)cq_e);
tx_comp_done++;
break;
case Q81_IOCB_RX:
ret = qls_rx_comp(ha, cq_idx, i, (q81_rx_t *)cq_e);
break;
case Q81_IOCB_MPI:
case Q81_IOCB_SYS:
default:
device_printf(ha->pci_dev, "%s[%d %d 0x%x]: illegal \n",
__func__, i, (*(ha->rx_ring[cq_idx].cqi_vaddr)),
cq_e->opcode);
qls_dump_buf32(ha, __func__, cq_e,
(sizeof (q81_cq_e_t) >> 2));
break;
}
i++;
if (i == NUM_CQ_ENTRIES)
i = 0;
if (ret) {
break;
}
if (i == cq_comp_idx) {
cq_comp_idx = *(ha->rx_ring[cq_idx].cqi_vaddr);
}
if (tx_comp_done) {
taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
tx_comp_done = 0;
}
}
while((!SLIST_EMPTY(&lro->lro_active))) {
queued = SLIST_FIRST(&lro->lro_active);
SLIST_REMOVE_HEAD(&lro->lro_active, next);
tcp_lro_flush(lro, queued);
}
ha->rx_ring[cq_idx].cq_next = cq_comp_idx;
if (!ret) {
Q81_WR_CQ_CONS_IDX(cq_idx, (ha->rx_ring[cq_idx].cq_next));
}
if (tx_comp_done)
taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
return;
}
static void
qls_mbx_isr(qla_host_t *ha)
{
uint32_t data;
int i;
device_t dev = ha->pci_dev;
if (qls_mbx_rd_reg(ha, 0, &data) == 0) {
if ((data & 0xF000) == 0x4000) {
ha->mbox[0] = data;
for (i = 1; i < Q81_NUM_MBX_REGISTERS; i++) {
if (qls_mbx_rd_reg(ha, i, &data))
break;
ha->mbox[i] = data;
}
ha->mbx_done = 1;
} else if ((data & 0xF000) == 0x8000) {
/* we have an AEN */
ha->aen[0] = data;
for (i = 1; i < Q81_NUM_AEN_REGISTERS; i++) {
if (qls_mbx_rd_reg(ha, i, &data))
break;
ha->aen[i] = data;
}
device_printf(dev,"%s: AEN "
"[0x%08x 0x%08x 0x%08x 0x%08x 0x%08x"
" 0x%08x 0x%08x 0x%08x 0x%08x]\n",
__func__,
ha->aen[0], ha->aen[1], ha->aen[2],
ha->aen[3], ha->aen[4], ha->aen[5],
ha->aen[6], ha->aen[7], ha->aen[8]);
switch ((ha->aen[0] & 0xFFFF)) {
case 0x8011:
ha->link_up = 1;
break;
case 0x8012:
ha->link_up = 0;
break;
case 0x8130:
ha->link_hw_info = ha->aen[1];
break;
case 0x8131:
ha->link_hw_info = 0;
break;
}
}
}
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);
return;
}
void
qls_isr(void *arg)
{
qla_ivec_t *ivec = arg;
qla_host_t *ha;
uint32_t status;
uint32_t cq_idx;
device_t dev;
ha = ivec->ha;
cq_idx = ivec->cq_idx;
dev = ha->pci_dev;
status = READ_REG32(ha, Q81_CTL_STATUS);
if (status & Q81_CTL_STATUS_FE) {
device_printf(dev, "%s fatal error\n", __func__);
return;
}
if ((cq_idx == 0) && (status & Q81_CTL_STATUS_PI)) {
qls_mbx_isr(ha);
}
status = READ_REG32(ha, Q81_CTL_INTR_STATUS1);
if (status & ( 0x1 << cq_idx))
qls_cq_isr(ha, cq_idx);
Q81_ENABLE_INTR(ha, cq_idx);
return;
}

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/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_os.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QLS_OS_H_
#define _QLS_OS_H_
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/mbuf.h>
#include <sys/protosw.h>
#include <sys/socket.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/kernel.h>
#include <sys/sockio.h>
#include <sys/types.h>
#include <machine/atomic.h>
#include <machine/_inttypes.h>
#include <sys/conf.h>
#if __FreeBSD_version < 900044
#error FreeBSD Version not supported - use version >= 900044
#endif
#include <net/if.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/bpf.h>
#include <net/if_types.h>
#include <net/if_vlan_var.h>
#include <netinet/in_systm.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <netinet/ip.h>
#include <netinet/ip6.h>
#include <netinet/tcp.h>
#include <netinet/udp.h>
#include <netinet/in_var.h>
#include <netinet/tcp_lro.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/proc.h>
#include <sys/sysctl.h>
#include <sys/endian.h>
#include <sys/taskqueue.h>
#include <sys/pcpu.h>
#include <sys/unistd.h>
#include <sys/kthread.h>
#include <machine/in_cksum.h>
#define QLA_USEC_DELAY(usec) DELAY(usec)
static __inline int qls_ms_to_hz(int ms)
{
int qla_hz;
struct timeval t;
t.tv_sec = ms / 1000;
t.tv_usec = (ms % 1000) * 1000;
qla_hz = tvtohz(&t);
if (qla_hz < 0)
qla_hz = 0x7fffffff;
if (!qla_hz)
qla_hz = 1;
return (qla_hz);
}
static __inline int qls_sec_to_hz(int sec)
{
struct timeval t;
t.tv_sec = sec;
t.tv_usec = 0;
return (tvtohz(&t));
}
#define qla_host_to_le16(x) htole16(x)
#define qla_host_to_le32(x) htole32(x)
#define qla_host_to_le64(x) htole64(x)
#define qla_host_to_be16(x) htobe16(x)
#define qla_host_to_be32(x) htobe32(x)
#define qla_host_to_be64(x) htobe64(x)
#define qla_le16_to_host(x) le16toh(x)
#define qla_le32_to_host(x) le32toh(x)
#define qla_le64_to_host(x) le64toh(x)
#define qla_be16_to_host(x) be16toh(x)
#define qla_be32_to_host(x) be32toh(x)
#define qla_be64_to_host(x) be64toh(x)
MALLOC_DECLARE(M_QLA8XXXBUF);
#define qls_mdelay(fn, msecs) \
{\
if (cold) \
DELAY((msecs * 1000)); \
else \
pause(fn, qls_ms_to_hz(msecs)); \
}
/*
* Locks
*/
#define QLA_LOCK(ha, str, no_delay) qls_lock(ha, str, no_delay)
#define QLA_UNLOCK(ha, str) qls_unlock(ha, str)
#define QLA_TX_LOCK(ha) mtx_lock(&ha->tx_lock);
#define QLA_TX_UNLOCK(ha) mtx_unlock(&ha->tx_lock);
#endif /* #ifndef _QLS_OS_H_ */

41
sys/dev/qlxge/qls_ver.h Normal file
View File

@ -0,0 +1,41 @@
/*
* Copyright (c) 2013-2014 Qlogic Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*/
/*
* File: qls_ver.h
* Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
*/
#ifndef _QLS_VER_H_
#define _QLS_VER_H_
#define QLA_VERSION_MAJOR 2
#define QLA_VERSION_MINOR 0
#define QLA_VERSION_BUILD 0
#endif /* #ifndef _QLS_VER_H_ */

2
sys/modules/Makefile
View File

@ -271,6 +271,7 @@ SUBDIR= \
${_pst} \
pty \
puc \
${_qlxge} \
${_qlxgb} \
${_qlxgbe} \
ral \
@ -713,6 +714,7 @@ _opensolaris= opensolaris
_padlock= padlock
.endif
_pccard= pccard
_qlxge= qlxge
_qlxgb= qlxgb
_qlxgbe= qlxgbe
_rdma= rdma

50
sys/modules/qlxge/Makefile Normal file
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@ -0,0 +1,50 @@
#/*
# * Copyright (c) 2013-2014 Qlogic Corporation
# * All rights reserved.
# *
# * Redistribution and use in source and binary forms, with or without
# * modification, are permitted provided that the following conditions
# * are met:
# *
# * 1. Redistributions of source code must retain the above copyright
# * notice, this list of conditions and the following disclaimer.
# * 2. Redistributions in binary form must reproduce the above copyright
# * notice, this list of conditions and the following disclaimer in the
# * documentation and/or other materials provided with the distribution.
# *
# * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
# * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# * POSSIBILITY OF SUCH DAMAGE.
# */
#/*
# * File : Makefile
# * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
# */
#
# $FreeBSD$
#
.PATH: ${.CURDIR}/../../dev/qlxge
KMOD=if_qlxge
SRCS=qls_os.c qls_dbg.c qls_hw.c qls_isr.c qls_dump.c
SRCS+=qls_ioctl.c
SRCS+= device_if.h bus_if.h pci_if.h
CFLAGS += -DQL_DBG
clean:
rm -f opt_bdg.h device_if.h bus_if.h pci_if.h export_syms
rm -f *.o *.kld *.ko
rm -f @ machine x86
.include <bsd.kmod.mk>