- Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds the header type. - Replace several magic numbers with appropriate constants for the header type register and a couple of PCI_FUNCMAX. - Merge to amd64 the fix to the i386 bridge code to skip devices with unknown header types. Requested by: imp (1, 2)
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@ -328,10 +328,18 @@ nexus_pcib_identify(driver_t *driver, device_t parent)
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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func = 0;
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hdrtype = nexus_pcib_read_config(0, bus, slot, func,
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PCIR_HEADERTYPE, 1);
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PCIR_HDRTYPE, 1);
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/*
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* When enumerating bus devices, the standard says that
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* one should check the header type and ignore the slots whose
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* header types that the software doesn't know about. We use
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* this to filter out devices.
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*/
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if ((hdrtype & PCIM_MFDEV) &&
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(!found_orion || hdrtype != 0xff))
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pcifunchigh = 7;
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pcifunchigh = PCI_FUNCMAX;
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else
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pcifunchigh = 0;
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for (func = 0; func <= pcifunchigh; func++) {
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@ -213,10 +213,10 @@ acpi_bus_number(ACPI_HANDLE root, ACPI_HANDLE curr, ACPI_PCI_ID *PciId)
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return (bus);
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subclass = pci_cfgregread(bus, slot, func, PCIR_SUBCLASS, 1);
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/* Find the header type, masking off the multifunction bit */
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header = pci_cfgregread(bus, slot, func, PCIR_HEADERTYPE, 1) & 0x7f;
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if (header == 1 && subclass == PCIS_BRIDGE_PCI)
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header = pci_cfgregread(bus, slot, func, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE;
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if (header == PCIM_HDRTYPE_BRIDGE && subclass == PCIS_BRIDGE_PCI)
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bus = pci_cfgregread(bus, slot, func, PCIR_SECBUS_1, 1);
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if (header == 2 && subclass == PCIS_BRIDGE_CARDBUS)
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if (header == PCIM_HDRTYPE_CARDBUS && subclass == PCIS_BRIDGE_CARDBUS)
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bus = pci_cfgregread(bus, slot, func, PCIR_SECBUS_2, 1);
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return (bus);
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}
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@ -354,7 +354,7 @@ pci_read_device(device_t pcib, int b, int s, int f, size_t size)
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cfg->subclass = REG(PCIR_SUBCLASS, 1);
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cfg->progif = REG(PCIR_PROGIF, 1);
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cfg->revid = REG(PCIR_REVID, 1);
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cfg->hdrtype = REG(PCIR_HEADERTYPE, 1);
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cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
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cfg->lattimer = REG(PCIR_LATTIMER, 1);
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cfg->intpin = REG(PCIR_INTPIN, 1);
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@ -834,8 +834,8 @@ pci_add_children(device_t dev, int busno, size_t dinfo_size)
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for (s = 0; s <= maxslots; s++) {
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pcifunchigh = 0;
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f = 0;
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hdrtype = REG(PCIR_HEADERTYPE, 1);
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if ((hdrtype & ~PCIM_MFDEV) > PCI_MAXHDRTYPE)
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hdrtype = REG(PCIR_HDRTYPE, 1);
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if (hdrtype & PCIM_MFDEV)
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pcifunchigh = PCI_FUNCMAX;
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@ -80,10 +80,11 @@
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#define PCIR_CLASS 0x0b
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#define PCIR_CACHELNSZ 0x0c
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#define PCIR_LATTIMER 0x0d
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#define PCIR_HEADERTYPE 0x0e
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#define PCIM_HEADERTYPE_NORMAL 0x00
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#define PCIM_HEADERTYPE_BRIDGE 0x01
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#define PCIM_HEADERTYPE_CARDBUS 0x02
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#define PCIR_HDRTYPE 0x0e
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#define PCIM_HDRTYPE 0x7f
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#define PCIM_HDRTYPE_NORMAL 0x00
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#define PCIM_HDRTYPE_BRIDGE 0x01
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#define PCIM_HDRTYPE_CARDBUS 0x02
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#define PCIM_MFDEV 0x80
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#define PCIR_BIST 0x0f
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@ -88,7 +88,7 @@ puc_pci_probe(device_t dev)
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uint32_t v1, v2, d1, d2;
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const struct puc_device_description *desc;
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if ((pci_read_config(dev, PCIR_HEADERTYPE, 1) & 0x7f) != 0)
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if ((pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) != 0)
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return (ENXIO);
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v1 = pci_read_config(dev, PCIR_VENDOR, 2);
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@ -322,18 +322,18 @@ legacy_pcib_identify(driver_t *driver, device_t parent)
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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func = 0;
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hdrtype = legacy_pcib_read_config(0, bus, slot, func,
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PCIR_HEADERTYPE, 1);
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PCIR_HDRTYPE, 1);
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/*
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* When enumerating bus devices, the standard says that
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* one should check the header type and ignore the slots whose
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* header types that the software doesn't know about. We use
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* this to filter out devices.
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*/
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if ((hdrtype & ~PCIM_MFDEV) > PCI_MAXHDRTYPE)
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if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
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continue;
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if ((hdrtype & PCIM_MFDEV) &&
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(!found_orion || hdrtype != 0xff))
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pcifunchigh = 7;
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pcifunchigh = PCI_FUNCMAX;
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else
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pcifunchigh = 0;
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for (func = 0; func <= pcifunchigh; func++) {
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