From 738eacb46bf6b9395ec6fbfaa04467d8da4223a1 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sat, 21 Oct 2017 19:14:45 +0000 Subject: [PATCH] Pull in r316035 from upstream llvm trunk (by Tim Northover): AArch64: account for possible frame index operand in compares. If the address of a local is used in a comparison, AArch64 can fold the address-calculation into the comparison via "adds". Unfortunately, a couple of places (both hit in this one test) are not ready to deal with that yet and just assume the first source operand is a register. This should fix an assertion failure while building the test suite of www/firefox for AArch64. PR: 223048 MFC after: 3 days --- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 6 ++++++ .../lib/Target/AArch64/AArch64RedundantCopyElimination.cpp | 3 +++ 2 files changed, 9 insertions(+) diff --git a/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index c0c6055c358f..13c80a46e5b0 100644 --- a/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -940,6 +940,12 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint( bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const { + // The first operand can be a frame index where we'd normally expect a + // register. + assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands"); + if (!MI.getOperand(1).isReg()) + return false; + switch (MI.getOpcode()) { default: break; diff --git a/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index 4e65c0ab6011..22c11c7276d2 100644 --- a/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRegValInBlock( // CMP is an alias for SUBS with a dead destination register. case AArch64::SUBSWri: case AArch64::SUBSXri: { + // Sometimes the first operand is a FrameIndex. Bail if tht happens. + if (!PredI.getOperand(1).isReg()) + return None; MCPhysReg SrcReg = PredI.getOperand(1).getReg(); // Must not be a symbolic immediate.