New ethernet device driver from Matt Thomas:
This driver supports all the DEC EtherWORKS III NICs (DE203, DE204, and DE205) and the later DEC EtherWORKS II NICs (DE200, DE201, DE202, DE422). DEPCA-style boards prior to the DE200 have not been tested and may not work. Submitted by: Matt Thomas (thomas@lkg.dec.com)
This commit is contained in:
David Greenman
parent
bd1671dc28
commit
7952584606
@ -1,7 +1,7 @@
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# This file tells config what files go into building a kernel,
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# files marked standard are always included.
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#
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# $Id: files.i386,v 1.32 1994/04/29 21:49:02 gclarkii Exp $
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# $Id: files.i386,v 1.34 1994/05/25 08:52:02 rgrimes Exp $
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#
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i386/i386/autoconf.c standard device-driver
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i386/i386/cons.c standard
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@ -31,6 +31,7 @@ i386/isa/if_ep.c optional ep device-driver
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i386/isa/if_ie.c optional ie device-driver
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i386/isa/if_is.c optional is device-driver
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i386/isa/if_ix.c optional ix device-driver
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i386/isa/if_le.c optional le device-driver
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i386/isa/isa.c optional isa device-driver
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i386/isa/lpa.c optional lpa device-driver
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i386/isa/lpt.c optional lpt device-driver
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@ -1,7 +1,7 @@
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# This file tells config what files go into building a kernel,
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# files marked standard are always included.
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#
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# $Id: files.i386,v 1.32 1994/04/29 21:49:02 gclarkii Exp $
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# $Id: files.i386,v 1.34 1994/05/25 08:52:02 rgrimes Exp $
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#
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i386/i386/autoconf.c standard device-driver
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i386/i386/cons.c standard
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@ -31,6 +31,7 @@ i386/isa/if_ep.c optional ep device-driver
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i386/isa/if_ie.c optional ie device-driver
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i386/isa/if_is.c optional is device-driver
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i386/isa/if_ix.c optional ix device-driver
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i386/isa/if_le.c optional le device-driver
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i386/isa/isa.c optional isa device-driver
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i386/isa/lpa.c optional lpa device-driver
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i386/isa/lpt.c optional lpt device-driver
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109
sys/i386/isa/ic/am7990.h
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109
sys/i386/isa/ic/am7990.h
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/*
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* AMD 7990 (LANCE) definitions
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*
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*
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*/
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#if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
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#define LN_BITFIELD2(a, b) b, a
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#define LN_BITFIELD3(a, b, c) c, b, a
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#define LN_BITFIELD4(a, b, c, d) d, c, b, a
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#else
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#define LN_BITFIELD2(a, b) a, b
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#define LN_BITFIELD3(a, b, c) a, b, c
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#define LN_BITFIELD4(a, b, c, d) a, b, c, d
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#endif
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#define LN_ADDR_LO(addr) ((addr) & 0xFFFF)
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#define LN_ADDR_HI(addr) (((addr) >> 16) & 0xFF)
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typedef struct {
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unsigned short r_addr_lo;
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unsigned short LN_BITFIELD3(r_addr_hi : 8,
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: 5,
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r_log2_size : 3);
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} ln_ring_t;
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#define LN_MC_MASK 0x3F /* Only 6 bits of the CRC */
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typedef struct {
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unsigned short ln_mode;
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#define LN_MODE_RXD 0x0001 /* ( W) Receiver Disabled */
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#define LN_MODE_TXD 0x0002 /* ( W) Transmitter Disabled */
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#define LN_MODE_LOOP 0x0004 /* ( W) Enable Loopback */
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#define LN_MODE_NOTXCRC 0x0008 /* ( W) Don't Calculate TX CRCs */
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#define LN_MODE_FRCCOLL 0x0010 /* ( W) Force Collision */
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#define LN_MODE_NORETRY 0x0020 /* ( W) No Transmit Retries */
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#define LN_MODE_INTLOOP 0x0040 /* ( W) Internal Loopback */
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#define LN_MODE_PROMISC 0x8000 /* ( W) Promiscious Mode */
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unsigned short ln_physaddr[3];
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unsigned short ln_multi_mask[4];
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ln_ring_t ln_rxring;
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ln_ring_t ln_txring;
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} ln_initb_t;
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typedef struct {
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unsigned short d_addr_lo;
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unsigned char d_addr_hi;
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unsigned char d_flag;
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#define LN_DFLAG_EOP 0x0001 /* (RW) End Of Packet */
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#define LN_DFLAG_SOP 0x0002 /* (RW) Start Of Packet */
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#define LN_DFLAG_RxBUFERROR 0x0004 /* (R ) Receive - Buffer Error */
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#define LN_DFLAG_TxDEFERRED 0x0004 /* (R ) Transmit - Initially Deferred */
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#define LN_DFLAG_RxBADCRC 0x0008 /* (R ) Receive - Bad Checksum */
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#define LN_DFLAG_TxONECOLL 0x0008 /* (R ) Transmit - Single Collision */
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#define LN_DFLAG_RxOVERFLOW 0x0010 /* (R ) Receive - Overflow Error */
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#define LN_DFLAG_TxMULTCOLL 0x0010 /* (R ) Transmit - Multiple Collisions */
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#define LN_DFLAG_RxFRAMING 0x0020 /* (R ) Receive - Framing Error */
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#define LN_DFLAG_RxERRSUM 0x0040 /* (R ) Receive - Error Summary */
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#define LN_DFLAG_TxERRSUM 0x0040 /* (R ) Transmit - Error Summary */
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#define LN_DFLAG_OWNER 0x0080 /* (RW) Owner (1=Am7990, 0=host) */
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signed short d_buflen; /* ( W) Two's complement */
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unsigned short d_status;
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#define LN_DSTS_RxLENMASK 0x0FFF /* (R ) Recieve Length */
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#define LN_DSTS_TxTDRMASK 0x03FF /* (R ) Transmit - Time Domain Reflectometer */
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#define LN_DSTS_TxEXCCOLL 0x0400 /* (R ) Transmit - Excessive Collisions */
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#define LN_DSTS_TxCARRLOSS 0x0800 /* (R ) Transmit - Carrier Loss */
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#define LN_DSTS_TxLATECOLL 0x1000 /* (R ) Transmit - Late Collision */
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#define LN_DSTS_TxUNDERFLOW 0x4000 /* (R ) Transmit - Underflow */
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#define LN_DSTS_TxBUFERROR 0x8000 /* (R ) Transmit - Buffer Error */
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} ln_desc_t;
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#define LN_CSR0 0x0000
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#define LN_CSR0_INIT 0x0001 /* (RS) Initialize Am 7990 */
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#define LN_CSR0_START 0x0002 /* (RS) Start Am7990 */
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#define LN_CSR0_STOP 0x0004 /* (RS) Reset Am7990 */
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#define LN_CSR0_TXDEMAND 0x0008 /* (RS) Transmit On Demand */
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#define LN_CSR0_TXON 0x0010 /* (R ) Transmitter Enabled */
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#define LN_CSR0_RXON 0x0020 /* (R ) Receiver Enabled */
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#define LN_CSR0_ENABINTR 0x0040 /* (RW) Interrupt Enabled */
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#define LN_CSR0_PENDINTR 0x0080 /* (R ) Interrupt Pending */
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#define LN_CSR0_INITDONE 0x0100 /* (RC) Initialization Done */
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#define LN_CSR0_TXINT 0x0200 /* (RC) Transmit Interrupt */
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#define LN_CSR0_RXINT 0x0400 /* (RC) Receive Interrupt */
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#define LN_CSR0_MEMERROR 0x0800 /* (RC) Memory Error */
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#define LN_CSR0_MISS 0x1000 /* (RC) No Available Receive Buffers */
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#define LN_CSR0_CERR 0x2000 /* (RC) SQE failed */
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#define LN_CSR0_BABL 0x4000 /* (RC) Transmit Babble */
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#define LN_CSR0_ERRSUM 0x8000 /* (R ) Error Summary (last 4) */
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#define LN_CSR0_CLEAR 0x7F00 /* Clear Status Bit */
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/*
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* CSR1 -- Init Block Address (Low 16 Bits -- Must be Word Aligned)
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* CSR2 -- Init Block Address (High 8 Bits)
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*/
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#define LN_CSR1 0x0001
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#define LN_CSR2 0x0002
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/*
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* CSR3 -- Hardware Control
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*/
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#define LN_CSR3 0x0003
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#define LN_CSR3_BCON 0x0001 /* (RW) BM/HOLD Control */
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#define LN_CSR3_ALE 0x0002 /* (RW) ALE Control */
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#define LN_CSR3_BSWP 0x0004 /* (RW) Byte Swap */
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177
sys/i386/isa/ic/lemac.h
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177
sys/i386/isa/ic/lemac.h
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/*
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* Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software withough specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: lemac.h,v 1.1 1994/08/01 16:03:42 thomas Exp $
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*/
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#ifndef _LEMAC_H_
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#define _LEMAC_H_
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/*
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* This is list of registers used on a DEC EtherWORKS III card.
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* Each board occupies a 32 byte register space. This can be
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* in either EISA or ISA space. Currently we only support ISA
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* space.
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*/
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#define LEMAC_REG_CS 0x00 /* Control and Status */
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#define LEMAC_REG_CTL 0x01 /* Control */
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#define LEMAC_REG_IC 0x02 /* Interrupt Control */
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#define LEMAC_REG_TS 0x03 /* Transmit Status */
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#define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */
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#define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */
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#define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */
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#define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */
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#define LEMAC_REG_RQ 0x08 /* Receive Queue */
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#define LEMAC_REG_RQC 0x09 /* Receive Queue Count */
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#define LEMAC_REG_TQ 0x0A /* Transmit Queue */
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#define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */
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#define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */
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#define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */
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#define LEMAC_REG_PI1 0x0E /* Page Index #1 */
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#define LEMAC_REG_PI2 0x0F /* Page Index #2 */
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#define LEMAC_REG_DAT 0x10 /* Data */
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#define LEMAC_REG_IOP 0x11 /* I/O Page */
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#define LEMAC_REG_IOB 0x12 /* I/O Base */
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#define LEMAC_REG_MPN 0x13 /* Memory Page */
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#define LEMAC_REG_MBR 0x14 /* Memory Base */
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#define LEMAC_REG_APD 0x15 /* Address PROM */
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#define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */
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#define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */
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#define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */
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#define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */
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#define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */
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#define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */
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#define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */
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#define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */
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#define LEMAC_REG_CNF 0x1E /* Configuration Management */
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#define LEMAC_IOSPACE 0x20 /* LEMAC uses 32 bytes of IOSPACE */
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#define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */
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#define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */
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#define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */
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#define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */
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#define LEMAC_REG_EIC 0x84 /* EISA Control */
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/* Control Page (Page 0) Definitions */
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#define LEMAC_MCTBL_BITS 9
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#define LEMAC_MCTBL_OFF 512
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#define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3))
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#define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */
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/* EEPROM Definitions */
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#define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */
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#define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */
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#define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */
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#define LEMAC_EEP_PRDNM 8 /* Product Name Offset */
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#define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */
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#define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */
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#define LEMAC_EEP_SETUP 23 /* Setup Options Offset */
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#define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */
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#define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */
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#define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */
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#define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */
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/* Receive Status Definitions */
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#define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */
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#define LEMAC_RX_CRC 0x02 /* CRC Error */
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#define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */
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#define LEMAC_RX_MCM 0x08 /* Multicast Match */
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#define LEMAC_RX_IAM 0x10 /* Individual Address Match */
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#define LEMAC_RX_OK 0x80 /* No Errors */
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/* Transmit Status Definitions (not valid if TXD == 0) */
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#define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */
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#define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */
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#define LEMAC_TS_LCL 0x20 /* Late collision of ... */
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#define LEMAC_TS_ID 0x40 /* Initially Deferred ... */
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/* Transmit Control Definitions */
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#define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */
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#define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */
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#define LEMAC_TX_PAD 0x04 /* Zero PAD to mininum length (yes) */
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#define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */
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#define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */
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#define LEMAC_TX_STP 0x20 /* Stop on Error (yes) */
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#define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */
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#define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\
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LEMAC_TX_STP|LEMAC_TX_SQE)
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#define LEMAC_TX_HDRSZ 4 /* Size of TX header */
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/* Transmit Done Queue Status Definitions */
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#define LEMAC_TDQ_COL 0x03 /* Collision Mask */
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#define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */
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#define LEMAC_TDQ_ONECOL 0x01 /* One Collision */
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#define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */
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#define LEMAC_TDQ_EXCCOL 0x03 /* Excesive Collisions */
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#define LEMAC_TDQ_ID 0x04 /* Initially Deferred */
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#define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */
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/* Control / Status Definitions */
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#define LEMAC_CS_RXD 0x01 /* Receiver Disabled */
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#define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */
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#define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */
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#define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */
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#define LEMAC_CS_MBZ4 0x10 /* MBZ */
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#define LEMAC_CS_MCE 0x20 /* Multicast Enable */
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#define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */
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#define LEMAC_CS_RA 0x80 /* Runt Accept */
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/* Control Definitions */
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#define LEMAC_CTL_LED 0x02 /* LED state (inverted) */
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/* Interrupt Control Definitions */
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#define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */
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#define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */
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#define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */
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#define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */
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#define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */
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#define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */
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#define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */
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#define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */
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#define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */
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#define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */
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#define LEMAC_IC_IE 0x80 /* Interrupt Enable */
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/* I/O Page Definitions */
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#define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */
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#define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */
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/* Configuration / Management Definitions */
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#define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */
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#endif /* _LEMAC_H_ */
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2144
sys/i386/isa/if_le.c
Normal file
2144
sys/i386/isa/if_le.c
Normal file
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