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Update llvm, clang, lld, lldb, compiler-rt and libc++ to release_39

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branch r288847.
This commit is contained in:
Dimitry Andric 2016-12-10 15:30:39 +00:00
commit 7a83c005f5
4 changed files with 32 additions and 20 deletions
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20
contrib/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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@ -718,13 +718,21 @@ bool AArch64ExpandPseudo::expandCMP_SWAP_128(
.addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
.addOperand(DesiredLo)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SBCSXr), AArch64::XZR)
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
.addReg(AArch64::WZR)
.addReg(AArch64::WZR)
.addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
.addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
.addOperand(DesiredHi);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
.addImm(AArch64CC::NE)
.addMBB(DoneBB)
.addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
.addOperand(DesiredHi)
.addImm(0);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
.addReg(StatusReg, RegState::Kill)
.addReg(StatusReg, RegState::Kill)
.addImm(AArch64CC::EQ);
BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
.addReg(StatusReg, RegState::Kill)
.addMBB(DoneBB);
LoadCmpBB->addSuccessor(DoneBB);
LoadCmpBB->addSuccessor(StoreBB);

19
contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -10083,17 +10083,24 @@ static void ReplaceReductionResults(SDNode *N,
Results.push_back(SplitVal);
}
static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
SDLoc DL(N);
SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N);
SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64,
DAG.getNode(ISD::SRL, DL, MVT::i128, N,
DAG.getConstant(64, DL, MVT::i64)));
return std::make_pair(Lo, Hi);
}
static void ReplaceCMP_SWAP_128Results(SDNode *N,
SmallVectorImpl<SDValue> & Results,
SelectionDAG &DAG) {
assert(N->getValueType(0) == MVT::i128 &&
"AtomicCmpSwap on types less than 128 should be legal");
SDValue Ops[] = {N->getOperand(1),
N->getOperand(2)->getOperand(0),
N->getOperand(2)->getOperand(1),
N->getOperand(3)->getOperand(0),
N->getOperand(3)->getOperand(1),
N->getOperand(0)};
auto Desired = splitInt128(N->getOperand(2), DAG);
auto New = splitInt128(N->getOperand(3), DAG);
SDValue Ops[] = {N->getOperand(1), Desired.first, Desired.second,
New.first, New.second, N->getOperand(0)};
SDNode *CmpSwap = DAG.getMachineNode(
AArch64::CMP_SWAP_128, SDLoc(N),
DAG.getVTList(MVT::i64, MVT::i64, MVT::i32, MVT::Other), Ops);

11
contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@ -932,13 +932,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
.addReg(DestLo, getKillRegState(Dest.isDead()))
.addReg(DesiredLo, getKillRegState(Desired.isDead())));
unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr;
MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr))
.addReg(StatusReg, RegState::Define | RegState::Dead)
.addReg(DestHi, getKillRegState(Dest.isDead()))
.addReg(DesiredHi, getKillRegState(Desired.isDead()));
AddDefaultPred(MIB);
MIB.addReg(ARM::CPSR, RegState::Kill);
BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
.addReg(DestHi, getKillRegState(Dest.isDead()))
.addReg(DesiredHi, getKillRegState(Desired.isDead()))
.addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
BuildMI(LoadCmpBB, DL, TII->get(Bcc))

2
lib/clang/include/clang/Basic/Version.inc
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@ -7,4 +7,4 @@
#define CLANG_VENDOR "FreeBSD "
#define SVN_REVISION "288513"
#define SVN_REVISION "288847"