o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.
o) Make the octeon_wdog driver work on multi-CPU systems and to also print more information on NMI that may aid debugging. Simplify and clean up internal API and structure.
This commit is contained in:
Juli Mallett
parent
5308af6337
commit
7b62328843
@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* Copyright (c) 2010-2011, Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -48,93 +49,98 @@ __FBSDID("$FreeBSD$");
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#define DEFAULT_TIMER_VAL 65535
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struct octeon_wdog_softc {
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device_t dev;
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/* XXX: replace with repscive CVMX_ constant */
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struct resource *irq_res[16];
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void *intr_hdl[16];
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int armed;
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int debug;
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device_t sc_dev;
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struct octeon_wdog_core_softc {
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int csc_core;
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struct resource *csc_intr;
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void *csc_intr_cookie;
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} sc_cores[MAXCPU];
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int sc_armed;
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int sc_debug;
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};
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extern void octeon_wdog_nmi_handler(void);
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void octeon_wdog_nmi(void);
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static void octeon_watchdog_arm_core(int core, unsigned long timer_val);
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static void octeon_watchdog_disarm_core(int core);
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static int octeon_wdog_attach(device_t dev);
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static void octeon_wdog_identify(driver_t *drv, device_t parent);
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static int octeon_wdog_intr(void *);;
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static int octeon_wdog_probe(device_t dev);
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static void octeon_wdog_setup(struct octeon_wdog_softc *sc, int cpu);
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static void octeon_wdog_sysctl(device_t dev);
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static void octeon_wdog_watchdog_fn(void *private, u_int cmd, int *error);
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static void octeon_watchdog_arm_core(int);
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static void octeon_watchdog_disarm_core(int);
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static int octeon_wdog_attach(device_t);
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static void octeon_wdog_identify(driver_t *, device_t);
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static int octeon_wdog_intr(void *);
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static int octeon_wdog_probe(device_t);
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static void octeon_wdog_setup(struct octeon_wdog_softc *, int);
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static void octeon_wdog_sysctl(device_t);
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static void octeon_wdog_watchdog_fn(void *, u_int, int *);
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void
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octeon_wdog_nmi()
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octeon_wdog_nmi(void)
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{
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int core;
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/* XXX: Add something useful here */
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printf("NMI detected\n");
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core = cvmx_get_core_num();
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/*
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* This is the end
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* Beautiful friend
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printf("cpu%u: NMI detected\n", core);
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printf("cpu%u: Exception PC: %p\n", core, (void *)mips_rd_excpc());
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printf("cpu%u: status %#x cause %#x\n", core, mips_rd_status(), mips_rd_cause());
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/*
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* This is the end
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* Beautiful friend
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*
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* Just wait for Soft Reset to come and take us
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*/
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for (;;)
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;
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continue;
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}
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static void
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octeon_watchdog_arm_core(int core, unsigned long timer_val)
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static void
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octeon_watchdog_arm_core(int core)
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{
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cvmx_ciu_wdogx_t ciu_wdog;
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/* Poke it! */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
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/*
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* XXX
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* Perhaps if KDB is enabled, we should use mode=2 and drop into the
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* debugger on NMI?
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*
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* XXX
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* Timer should be calculated based on CPU frquency
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*/
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ciu_wdog.u64 = 0;
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ciu_wdog.s.len = timer_val;
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ciu_wdog.s.len = DEFAULT_TIMER_VAL;
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ciu_wdog.s.mode = 3;
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cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
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}
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static void
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static void
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octeon_watchdog_disarm_core(int core)
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{
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cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
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}
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static void
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octeon_wdog_watchdog_fn(void *private, u_int cmd, int *error)
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{
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struct octeon_wdog_softc *sc = private;
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uint64_t timer_val = 0;
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int core;
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cmd &= WD_INTERVAL;
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if (sc->debug)
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device_printf(sc->dev, "octeon_wdog_watchdog_fn: cmd: %x\n", cmd);
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if (sc->sc_debug)
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device_printf(sc->sc_dev, "%s: cmd: %x\n", __func__, cmd);
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if (cmd > 0) {
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if (sc->debug)
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device_printf(sc->dev, "octeon_wdog_watchdog_fn: programming timer: %jx\n", (uintmax_t) timer_val);
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/*
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* XXX: This should be done for every core and with value
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* calculated based on CPU frquency
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*/
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octeon_watchdog_arm_core(cvmx_get_core_num(), DEFAULT_TIMER_VAL);
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sc->armed = 1;
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CPU_FOREACH(core)
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octeon_watchdog_arm_core(core);
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sc->sc_armed = 1;
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*error = 0;
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} else {
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if (sc->debug)
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device_printf(sc->dev, "octeon_wdog_watchdog_fn: disarming\n");
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if (sc->armed) {
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sc->armed = 0;
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/* XXX: This should be done for every core */
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octeon_watchdog_disarm_core(cvmx_get_core_num());
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if (sc->sc_armed) {
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CPU_FOREACH(core)
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octeon_watchdog_disarm_core(core);
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sc->sc_armed = 0;
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}
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}
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}
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@ -144,54 +150,64 @@ octeon_wdog_sysctl(device_t dev)
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{
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struct octeon_wdog_softc *sc = device_get_softc(dev);
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struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
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struct sysctl_oid *tree = device_get_sysctl_tree(sc->dev);
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struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
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struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
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SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"debug", CTLFLAG_RW, &sc->debug, 0,
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"debug", CTLFLAG_RW, &sc->sc_debug, 0,
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"enable watchdog debugging");
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SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"armed", CTLFLAG_RD, &sc->armed, 0,
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"armed", CTLFLAG_RD, &sc->sc_armed, 0,
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"whether the watchdog is armed");
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}
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static void
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octeon_wdog_setup(struct octeon_wdog_softc *sc, int cpu)
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octeon_wdog_setup(struct octeon_wdog_softc *sc, int core)
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{
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int core, rid, err;
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struct octeon_wdog_core_softc *csc;
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int rid, error;
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/* XXX: map cpu id to core here ? */
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core = cvmx_get_core_num();
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csc = &sc->sc_cores[core];
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csc->csc_core = core;
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/* Interrupt part */
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rid = 0;
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sc->irq_res[core] =
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bus_alloc_resource(sc->dev, SYS_RES_IRQ, &rid,
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CVMX_IRQ_WDOG0+core,
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CVMX_IRQ_WDOG0+core, 1, RF_ACTIVE);
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if (!(sc->irq_res[core]))
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goto error;
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csc->csc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
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CVMX_IRQ_WDOG0 + core, CVMX_IRQ_WDOG0 + core, 1, RF_ACTIVE);
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if (csc->csc_intr == NULL)
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panic("%s: bus_alloc_resource for core %u failed",
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__func__, core);
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err = bus_setup_intr(sc->dev, sc->irq_res[core], INTR_TYPE_MISC,
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octeon_wdog_intr, NULL, sc, &sc->intr_hdl[core]);
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if (err)
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goto error;
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error = bus_setup_intr(sc->sc_dev, csc->csc_intr, INTR_TYPE_MISC,
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octeon_wdog_intr, NULL, csc, &csc->csc_intr_cookie);
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if (error != 0)
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panic("%s: bus_setup_intr for core %u: %d", __func__, core,
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error);
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/* XXX: pin interrupt handler to the respective core */
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bus_bind_intr(sc->sc_dev, csc->csc_intr, core);
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bus_describe_intr(sc->sc_dev, csc->csc_intr, csc->csc_intr_cookie,
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"cpu%u", core);
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/* Disarm by default */
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octeon_watchdog_disarm_core(core);
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return;
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error:
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panic("failed to setup watchdog interrupt for core %d", core);
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if (sc->sc_armed) {
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/* Armed by default. */
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octeon_watchdog_arm_core(core);
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} else {
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/* Disarmed by default. */
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octeon_watchdog_disarm_core(core);
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}
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}
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static int
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octeon_wdog_intr(void *sc)
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octeon_wdog_intr(void *arg)
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{
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struct octeon_wdog_core_softc *csc = arg;
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KASSERT(csc->csc_core == cvmx_get_core_num(),
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("got watchdog interrupt for core %u on core %u.",
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csc->csc_core, cvmx_get_core_num()));
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(void)csc;
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/* Poke it! */
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cvmx_write_csr(CVMX_CIU_PP_POKEX(cvmx_get_core_num()), 1);
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@ -211,14 +227,14 @@ static int
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octeon_wdog_attach(device_t dev)
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{
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struct octeon_wdog_softc *sc = device_get_softc(dev);
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int i;
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uint64_t *nmi_handler = (uint64_t*)octeon_wdog_nmi_handler;
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/* Initialise */
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sc->armed = 0;
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sc->debug = 0;
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int core, i;
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sc->dev = dev;
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/* Initialise */
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sc->sc_armed = 0; /* XXX Ought to be a tunable / config option. */
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sc->sc_debug = 0;
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sc->sc_dev = dev;
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EVENTHANDLER_REGISTER(watchdog_list, octeon_wdog_watchdog_fn, sc, 0);
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octeon_wdog_sysctl(dev);
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@ -229,8 +245,8 @@ octeon_wdog_attach(device_t dev)
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cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
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/* XXX: This should be done for every core */
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octeon_wdog_setup(sc, cvmx_get_core_num());
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CPU_FOREACH(core)
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octeon_wdog_setup(sc, core);
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return (0);
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}
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@ -108,6 +108,11 @@ mips_write_membar(void)
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}
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#ifdef _KERNEL
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/*
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* XXX
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* It would be nice to add variants that read/write register_t, to avoid some
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* ABI checks.
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*/
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#if defined(__mips_n32) || defined(__mips_n64)
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#define MIPS_RDRW64_COP0(n,r) \
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static __inline uint64_t \
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@ -132,6 +137,7 @@ mips_wr_ ## n (uint64_t a0) \
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} struct __hack
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#if defined(__mips_n64)
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MIPS_RDRW64_COP0(excpc, MIPS_COP_0_EXC_PC);
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MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
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MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
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MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
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@ -208,6 +214,9 @@ MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
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MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
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MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
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MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
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#if !defined(__mips_n64)
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MIPS_RDWR32_COP0(excpc, MIPS_COP_0_EXC_PC);
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#endif
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MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
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/* XXX: Some of these registers are specific to MIPS32. */
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