Modify handling of writes to the vlapic LVT registers.
The handler is now called after the register value is updated in the virtual APIC page. This will make it easier to handle APIC-write VM-exits with APIC register virtualization turned on. This also implies that we need to keep a snapshot of the last value written to a LVT register. We can no longer rely on the LVT registers in the APIC page to be "clean" because the guest can write anything to it before the hypervisor has had a chance to sanitize it.
This commit is contained in:
Neel Natu
parent
b2c730e011
commit
7c05bc3124
@ -94,7 +94,6 @@ do { \
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#define PRIO(x) ((x) >> 4)
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#define VLAPIC_VERSION (16)
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#define VLAPIC_MAXLVT_ENTRIES (APIC_LVT_CMCI)
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#define x2apic(vlapic) (((vlapic)->msr_apicbase & APICBASE_X2APIC) ? 1 : 0)
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@ -212,20 +211,6 @@ vlapic_timer_divisor(uint32_t dcr)
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}
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}
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static void
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vlapic_mask_lvts(struct vlapic *vlapic)
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{
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struct LAPIC *lapic = vlapic->apic_page;
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lapic->lvt_cmci |= APIC_LVT_M;
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lapic->lvt_timer |= APIC_LVT_M;
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lapic->lvt_thermal |= APIC_LVT_M;
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lapic->lvt_pcint |= APIC_LVT_M;
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lapic->lvt_lint0 |= APIC_LVT_M;
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lapic->lvt_lint1 |= APIC_LVT_M;
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lapic->lvt_error |= APIC_LVT_M;
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}
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#if 0
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static inline void
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vlapic_dump_lvt(uint32_t offset, uint32_t *lvt)
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@ -304,32 +289,6 @@ vlapic_esr_write_handler(struct vlapic *vlapic)
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vlapic->esr_pending = 0;
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}
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static void
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vlapic_reset(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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lapic = vlapic->apic_page;
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bzero(lapic, sizeof(struct LAPIC));
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lapic->id = vlapic_get_id(vlapic);
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lapic->version = VLAPIC_VERSION;
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lapic->version |= (VLAPIC_MAXLVT_ENTRIES << MAXLVTSHIFT);
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lapic->dfr = 0xffffffff;
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lapic->svr = APIC_SVR_VECTOR;
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vlapic_mask_lvts(vlapic);
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lapic->dcr_timer = 0;
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vlapic_dcr_write_handler(vlapic);
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if (vlapic->vcpuid == 0)
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vlapic->boot_state = BS_RUNNING; /* BSP */
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else
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vlapic->boot_state = BS_INIT; /* AP */
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vlapic->svr_last = lapic->svr;
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}
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void
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vlapic_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
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{
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@ -388,24 +347,65 @@ vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset)
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}
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}
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static __inline int
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lvt_off_to_idx(uint32_t offset)
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{
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int index;
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switch (offset) {
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case APIC_OFFSET_CMCI_LVT:
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index = APIC_LVT_CMCI;
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break;
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case APIC_OFFSET_TIMER_LVT:
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index = APIC_LVT_TIMER;
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break;
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case APIC_OFFSET_THERM_LVT:
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index = APIC_LVT_THERMAL;
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break;
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case APIC_OFFSET_PERF_LVT:
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index = APIC_LVT_PMC;
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break;
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case APIC_OFFSET_LINT0_LVT:
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index = APIC_LVT_LINT0;
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break;
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case APIC_OFFSET_LINT1_LVT:
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index = APIC_LVT_LINT1;
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break;
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case APIC_OFFSET_ERROR_LVT:
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index = APIC_LVT_ERROR;
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break;
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default:
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index = -1;
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break;
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}
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KASSERT(index >= 0 && index <= VLAPIC_MAXLVT_INDEX, ("lvt_off_to_idx: "
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"invalid lvt index %d for offset %#x", index, offset));
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return (index);
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}
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static __inline uint32_t
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vlapic_get_lvt(struct vlapic *vlapic, uint32_t offset)
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{
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int idx;
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uint32_t val;
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return (*vlapic_get_lvtptr(vlapic, offset));
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idx = lvt_off_to_idx(offset);
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val = atomic_load_acq_32(&vlapic->lvt_last[idx]);
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return (val);
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}
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static void
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vlapic_set_lvt(struct vlapic *vlapic, uint32_t offset, uint32_t val)
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void
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vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
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{
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uint32_t *lvtptr, mask;
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uint32_t *lvtptr, mask, val;
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struct LAPIC *lapic;
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int idx;
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lapic = vlapic->apic_page;
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lvtptr = vlapic_get_lvtptr(vlapic, offset);
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if (offset == APIC_OFFSET_TIMER_LVT)
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VLAPIC_TIMER_LOCK(vlapic);
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val = *lvtptr;
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idx = lvt_off_to_idx(offset);
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if (!(lapic->svr & APIC_SVR_ENABLE))
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val |= APIC_LVT_M;
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@ -424,10 +424,36 @@ vlapic_set_lvt(struct vlapic *vlapic, uint32_t offset, uint32_t val)
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mask |= APIC_LVT_DM;
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break;
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}
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*lvtptr = val & mask;
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val &= mask;
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*lvtptr = val;
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atomic_store_rel_32(&vlapic->lvt_last[idx], val);
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}
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if (offset == APIC_OFFSET_TIMER_LVT)
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VLAPIC_TIMER_UNLOCK(vlapic);
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static void
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vlapic_mask_lvts(struct vlapic *vlapic)
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{
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struct LAPIC *lapic = vlapic->apic_page;
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lapic->lvt_cmci |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
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lapic->lvt_timer |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);
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lapic->lvt_thermal |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);
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lapic->lvt_pcint |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);
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lapic->lvt_lint0 |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);
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lapic->lvt_lint1 |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);
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lapic->lvt_error |= APIC_LVT_M;
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vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);
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}
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static int
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@ -648,7 +674,7 @@ vlapic_fire_cmci(struct vlapic *vlapic)
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}
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}
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static VMM_STAT_ARRAY(LVTS_TRIGGERRED, VLAPIC_MAXLVT_ENTRIES,
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static VMM_STAT_ARRAY(LVTS_TRIGGERRED, VLAPIC_MAXLVT_INDEX + 1,
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"lvts triggered");
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int
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@ -1166,6 +1192,11 @@ vlapic_read(struct vlapic *vlapic, uint64_t offset, uint64_t *data, bool *retu)
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case APIC_OFFSET_CMCI_LVT:
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case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
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*data = vlapic_get_lvt(vlapic, offset);
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#ifdef INVARIANTS
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reg = vlapic_get_lvtptr(vlapic, offset);
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KASSERT(*data == *reg, ("inconsistent lvt value at "
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"offset %#lx: %#lx/%#x", offset, *data, *reg));
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#endif
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break;
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case APIC_OFFSET_TIMER_ICR:
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*data = lapic->icr_timer;
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@ -1190,6 +1221,7 @@ int
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vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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{
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struct LAPIC *lapic = vlapic->apic_page;
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uint32_t *regptr;
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int retval;
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KASSERT((offset & 0xf) == 0 && offset < PAGE_SIZE,
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@ -1238,7 +1270,9 @@ vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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break;
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case APIC_OFFSET_CMCI_LVT:
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case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
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vlapic_set_lvt(vlapic, offset, data);
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regptr = vlapic_get_lvtptr(vlapic, offset);
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*regptr = data;
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vlapic_lvt_write_handler(vlapic, offset);
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break;
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case APIC_OFFSET_TIMER_ICR:
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lapic->icr_timer = data;
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@ -1269,6 +1303,32 @@ vlapic_write(struct vlapic *vlapic, uint64_t offset, uint64_t data, bool *retu)
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return (retval);
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}
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static void
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vlapic_reset(struct vlapic *vlapic)
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{
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struct LAPIC *lapic;
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lapic = vlapic->apic_page;
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bzero(lapic, sizeof(struct LAPIC));
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lapic->id = vlapic_get_id(vlapic);
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lapic->version = VLAPIC_VERSION;
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lapic->version |= (VLAPIC_MAXLVT_INDEX << MAXLVTSHIFT);
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lapic->dfr = 0xffffffff;
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lapic->svr = APIC_SVR_VECTOR;
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vlapic_mask_lvts(vlapic);
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lapic->dcr_timer = 0;
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vlapic_dcr_write_handler(vlapic);
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if (vlapic->vcpuid == 0)
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vlapic->boot_state = BS_RUNNING; /* BSP */
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else
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vlapic->boot_state = BS_INIT; /* AP */
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vlapic->svr_last = lapic->svr;
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}
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void
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vlapic_init(struct vlapic *vlapic)
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{
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@ -80,4 +80,5 @@ void vlapic_esr_write_handler(struct vlapic *vlapic);
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int vlapic_icrlo_write_handler(struct vlapic *vlapic, bool *retu);
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void vlapic_icrtmr_write_handler(struct vlapic *vlapic);
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void vlapic_dcr_write_handler(struct vlapic *vlapic);
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void vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset);
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#endif /* _VLAPIC_H_ */
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@ -29,6 +29,8 @@
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#ifndef _VLAPIC_PRIV_H_
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#define _VLAPIC_PRIV_H_
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#include <x86/apicreg.h>
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/*
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* APIC Register: Offset Description
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*/
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@ -91,6 +93,8 @@ enum boot_state {
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*/
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#define ISRVEC_STK_SIZE (16 + 1)
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#define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI
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struct vlapic {
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struct vm *vm;
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int vcpuid;
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@ -111,12 +115,20 @@ struct vlapic {
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* The vector on the top of the stack is used to compute the
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* Processor Priority in conjunction with the TPR.
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*/
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uint8_t isrvec_stk[ISRVEC_STK_SIZE];
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int isrvec_stk_top;
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uint8_t isrvec_stk[ISRVEC_STK_SIZE];
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int isrvec_stk_top;
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uint64_t msr_apicbase;
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enum boot_state boot_state;
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uint32_t svr_last;
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uint64_t msr_apicbase;
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enum boot_state boot_state;
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/*
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* Copies of some registers in the virtual APIC page. We do this for
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* a couple of different reasons:
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* - to be able to detect what changed (e.g. svr_last)
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* - to maintain a coherent snapshot of the register (e.g. lvt_last)
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*/
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uint32_t svr_last;
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uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1];
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};
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void vlapic_init(struct vlapic *vlapic);
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