Was chasing down a failure to load f/w on a 2400. It turns out that the card
is actually broken, or needs a BIOS upgrade for 64 bit loads, but this uncovered a couple of misplaced opcode definitions and some missing continual mbox command cases, so might as well update them here.
This commit is contained in:
Matt Jacob
parent
dcc20f4b7f
commit
7d3cea3137
@ -748,11 +748,13 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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if (dodnld && IS_24XX(isp)) {
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const uint32_t *ptr = isp->isp_mdvec->dv_ispfw;
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int wordload;
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/*
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* Keep loading until we run out of f/w.
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*/
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code_org = ptr[2]; /* 1st load address is our start addr */
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wordload = 0;
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for (;;) {
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uint32_t la, wi, wl;
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@ -777,6 +779,7 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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wl--;
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}
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MEMORYBARRIER(isp, SYNC_REQUEST, 0, ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)), -1);
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again:
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ISP_MEMZERO(&mbs, sizeof (mbs));
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if (la < 0x10000 && nw < 0x10000) {
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mbs.param[0] = MBOX_LOAD_RISC_RAM_2100;
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@ -786,6 +789,23 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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mbs.param[4] = nw;
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mbs.param[6] = DMA_WD3(isp->isp_rquest_dma);
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mbs.param[7] = DMA_WD2(isp->isp_rquest_dma);
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isp_prt(isp, ISP_LOGDEBUG0, "LOAD RISC RAM 2100 %u words at load address 0x%x", nw, la);
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} else if (wordload) {
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union {
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const uint32_t *cp;
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uint32_t *np;
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} ucd;
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ucd.cp = (const uint32_t *)cp;
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mbs.param[0] = MBOX_WRITE_RAM_WORD_EXTENDED;
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mbs.param[1] = la;
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mbs.param[2] = (*ucd.np);
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mbs.param[3] = (*ucd.np) >> 16;
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mbs.param[8] = la >> 16;
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isp->isp_mbxwrk0 = nw - 1;
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isp->isp_mbxworkp = ucd.np+1;
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isp->isp_mbxwrk1 = (la + 1);
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isp->isp_mbxwrk8 = (la + 1) >> 16;
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isp_prt(isp, ISP_LOGDEBUG0, "WRITE RAM WORD EXTENDED %u words at load address 0x%x", nw, la);
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} else {
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mbs.param[0] = MBOX_LOAD_RISC_RAM;
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mbs.param[1] = la;
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@ -796,10 +816,16 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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mbs.param[6] = DMA_WD3(isp->isp_rquest_dma);
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mbs.param[7] = DMA_WD2(isp->isp_rquest_dma);
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mbs.param[8] = la >> 16;
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isp_prt(isp, ISP_LOGDEBUG0, "LOAD RISC RAM %u words at load address 0x%x", nw, la);
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}
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mbs.logval = MBLOGALL;
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isp_mboxcmd(isp, &mbs);
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if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
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if (mbs.param[0] == MBOX_HOST_INTERFACE_ERROR) {
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isp_prt(isp, ISP_LOGERR, "switching to word load");
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wordload = 1;
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goto again;
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}
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isp_prt(isp, ISP_LOGERR, "F/W Risc Ram Load Failed");
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ISP_RESET0(isp);
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return;
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@ -855,6 +881,7 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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mbs.param[4] = nw;
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mbs.param[6] = DMA_WD3(isp->isp_rquest_dma);
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mbs.param[7] = DMA_WD2(isp->isp_rquest_dma);
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isp_prt(isp, ISP_LOGDEBUG1, "LOAD RISC RAM 2100 %u words at load address 0x%x\n", nw, la);
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} else {
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mbs.param[0] = MBOX_LOAD_RISC_RAM;
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mbs.param[1] = la;
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@ -864,6 +891,7 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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mbs.param[6] = DMA_WD3(isp->isp_rquest_dma);
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mbs.param[7] = DMA_WD2(isp->isp_rquest_dma);
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mbs.param[8] = la >> 16;
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isp_prt(isp, ISP_LOGDEBUG1, "LOAD RISC RAM %u words at load address 0x%x\n", nw, la);
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}
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mbs.logval = MBLOGALL;
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isp_mboxcmd(isp, &mbs);
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@ -910,6 +938,7 @@ isp_reset(ispsoftc_t *isp, int do_load_defaults)
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mbs.param[1] = code_org;
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mbs.param[2] = ucd.np[0];
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mbs.logval = MBLOGNONE;
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isp_prt(isp, ISP_LOGDEBUG1, "WRITE RAM %u words at load address 0x%x\n", ucd.np[3], code_org);
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isp_mboxcmd(isp, &mbs);
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if (mbs.param[0] != MBOX_COMMAND_COMPLETE) {
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isp_prt(isp, ISP_LOGERR, "F/W download failed at word %d", isp->isp_mbxwrk1 - code_org);
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@ -6589,23 +6618,39 @@ isp_mbox_continue(ispsoftc_t *isp)
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mbs.param[1] = isp->isp_mbxwrk1++;
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break;
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case MBOX_WRITE_RAM_WORD_EXTENDED:
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if (IS_24XX(isp)) {
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uint32_t *lptr = (uint32_t *)ptr;
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mbs.param[2] = lptr[0];
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mbs.param[3] = lptr[0] >> 16;
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lptr++;
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ptr = (uint16_t *)lptr;
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} else {
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mbs.param[2] = *ptr++;
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}
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offset = isp->isp_mbxwrk1;
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offset |= isp->isp_mbxwrk8 << 16;
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mbs.param[2] = *ptr++;
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mbs.param[1] = offset;
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mbs.param[8] = offset >> 16;
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isp->isp_mbxwrk1 = ++offset;
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offset++;
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isp->isp_mbxwrk1 = offset;
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isp->isp_mbxwrk8 = offset >> 16;
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break;
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case MBOX_READ_RAM_WORD_EXTENDED:
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if (IS_24XX(isp)) {
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uint32_t *lptr = (uint32_t *)ptr;
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uint32_t val = isp->isp_mboxtmp[2];
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val |= (isp->isp_mboxtmp[3]) << 16;
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*lptr++ = val;
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ptr = (uint16_t *)lptr;
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} else {
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*ptr++ = isp->isp_mboxtmp[2];
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}
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offset = isp->isp_mbxwrk1;
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offset |= isp->isp_mbxwrk8 << 16;
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*ptr++ = isp->isp_mboxtmp[2];
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mbs.param[1] = offset;
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mbs.param[8] = offset >> 16;
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isp->isp_mbxwrk1 = ++offset;
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offset++;
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isp->isp_mbxwrk1 = offset;
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isp->isp_mbxwrk8 = offset >> 16;
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break;
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}
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@ -6830,7 +6875,7 @@ static const uint32_t mbpfc[] = {
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ISPOPMAP(0x00, 0x00), /* 0x0c: */
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ISPOPMAP(0x10f, 0x01), /* 0x0d: MBOX_WRITE_RAM_WORD_EXTENDED */
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ISPOPMAP(0x01, 0x05), /* 0x0e: MBOX_CHECK_FIRMWARE */
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ISPOPMAP(0x10f, 0x05), /* 0x0f: MBOX_READ_RAM_WORD_EXTENDED */
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ISPOPMAP(0x103, 0x0d), /* 0x0f: MBOX_READ_RAM_WORD_EXTENDED */
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ISPOPMAP(0x1f, 0x11), /* 0x10: MBOX_INIT_REQ_QUEUE */
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ISPOPMAP(0x2f, 0x21), /* 0x11: MBOX_INIT_RES_QUEUE */
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ISPOPMAP(0x0f, 0x01), /* 0x12: MBOX_EXECUTE_IOCB */
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@ -6962,13 +7007,13 @@ static const char *fc_mbcmd_names[] = {
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"MAILBOX REG TEST",
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"VERIFY CHECKSUM",
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"ABOUT FIRMWARE",
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"LOAD RAM",
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"LOAD RAM (2100)",
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"DUMP RAM",
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"LOAD RISC RAM",
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NULL,
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"WRITE RAM WORD EXTENDED",
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NULL,
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"READ RAM WORD EXTENDED",
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"CHECK FIRMWARE",
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NULL,
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"READ RAM WORD EXTENDED",
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"INIT REQUEST QUEUE",
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"INIT RESULT QUEUE",
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"EXECUTE IOCB",
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@ -1458,6 +1458,7 @@ imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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imushp->error = EINVAL;
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return;
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}
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isp_prt(imushp->isp, ISP_LOGDEBUG0, "request/result area @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
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imushp->isp->isp_rquest = imushp->vbase;
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imushp->isp->isp_rquest_dma = segs->ds_addr;
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segs->ds_addr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(imushp->isp));
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@ -1487,6 +1488,7 @@ imc1(void *arg, bus_dma_segment_t *segs, int nseg, int error)
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imushp->error = EINVAL;
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return;
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}
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isp_prt(imushp->isp, ISP_LOGDEBUG0, "scdma @ 0x%jx/0x%jx", (uintmax_t) segs->ds_addr, (uintmax_t) segs->ds_len);
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FCPARAM(imushp->isp, imushp->chan)->isp_scdma = segs->ds_addr;
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FCPARAM(imushp->isp, imushp->chan)->isp_scratch = imushp->vbase;
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}
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