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powerpc: Add lwsync and ptesync 'sync' opcode variants to ddb disassembler

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The canonical form of sync is:

  sync L, E (if Category Elemental Memory Barriers implemented)

The L bits (2) denote the type of sync:

  0 -- hwsync
  1 -- lwsync
  2 -- ptesync or hwsync

It's been found that most 32-bit CPUs designed prior to the introduction of
lwsync will ignore the L bits.  However, some cores, particularly the e500 core,
will trigger an illegal instruction exception.  Adding these variants will make
it easier to see which sync variant is actually being used in case of a trap.
This commit is contained in:
Justin Hibbits 2018-08-10 03:28:40 +00:00
parent 79476a1c3e
commit 7d849dc1a4
1 changed files with 3 additions and 1 deletions
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4
sys/powerpc/powerpc/db_disasm.c
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@ -310,7 +310,9 @@ const struct opcode opcodes_1f[] = {
{ "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B },
{ "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR },
{ "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB },
{ "sync", 0xfc0007fe, 0x7c0004ac, 0 },
{ "sync", 0xfc6007fe, 0x7c0004ac, 0 },
{ "lwsync", 0xfc6007fe, 0x7c2004ac, 0 },
{ "ptesync", 0xfc6007fe, 0x7c4004ac, 0 },
{ "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B },
{ "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B },
{ "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B },