Implement PHY bus MMD writes for arswitch.

This is used by the AR8327 PHY setup path.

Obtained from:	OpenWRT

sys/dev/etherswitch/arswitch/arswitch_reg.c

@@ -111,6 +111,16 @@ arswitch_writedbg(device_t dev, int phy, uint16_t dbg_addr,
 	    MII_ATH_DBG_DATA, dbg_data);
 }
 
+void
+arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,
+    uint16_t dbg_data)
+{
+	(void) MDIO_WRITEREG(device_get_parent(dev), phy,
+	    MII_ATH_MMD_ADDR, dbg_addr);
+	(void) MDIO_WRITEREG(device_get_parent(dev), phy,
+	    MII_ATH_MMD_DATA, dbg_data);
+}
+
 /*
  * Write half a register
  */

sys/dev/etherswitch/arswitch/arswitchreg.h

@@ -39,6 +39,8 @@
 #define	MS(_v, _f)	(((_v) & (_f)) >> _f##_S)
 
 /* Atheros specific MII registers */
+#define	MII_ATH_MMD_ADDR		0x0d
+#define	MII_ATH_MMD_DATA		0x0e
 #define	MII_ATH_DBG_ADDR		0x1d
 #define	MII_ATH_DBG_DATA		0x1e