Fix some more overly long lines, whitespace and other bugs according to
style(9) as well as spelling in comments.
This commit is contained in:
Marius Strobl
parent
5fca242374
commit
7e6ccea3b1
@ -111,14 +111,15 @@ struct mmc_ivars {
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char card_sn_string[16];/* Formatted serial # for disk->d_ident */
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};
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#define CMD_RETRIES 3
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#define CMD_RETRIES 3
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#define CARD_ID_FREQUENCY 400000 /* Spec requires 400kHz max during ID phase. */
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static SYSCTL_NODE(_hw, OID_AUTO, mmc, CTLFLAG_RD, NULL, "mmc driver");
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static int mmc_debug;
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SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0, "Debug level");
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SYSCTL_INT(_hw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &mmc_debug, 0,
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"Debug level");
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/* bus entry points */
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static int mmc_acquire_bus(device_t busdev, device_t dev);
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@ -137,14 +138,14 @@ static int mmc_wait_for_request(device_t brdev, device_t reqdev,
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static int mmc_write_ivar(device_t bus, device_t child, int which,
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uintptr_t value);
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#define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define MMC_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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#define MMC_LOCK_INIT(_sc) \
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mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->dev), \
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"mmc", MTX_DEF)
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#define MMC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define MMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx);
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#define MMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED);
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#define MMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED);
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static int mmc_all_send_cid(struct mmc_softc *sc, uint32_t *rawcid);
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static void mmc_app_decode_scr(uint32_t *raw_scr, struct mmc_scr *scr);
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@ -744,9 +745,9 @@ mmc_set_card_bus_width(struct mmc_softc *sc, uint16_t rca, int width)
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static int
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mmc_set_timing(struct mmc_softc *sc, int timing)
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{
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u_char switch_res[64];
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int err;
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uint8_t value;
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u_char switch_res[64];
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switch (timing) {
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case bus_timing_normal:
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@ -1161,9 +1162,9 @@ mmc_app_send_scr(struct mmc_softc *sc, uint16_t rca, uint32_t *rawscr)
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static int
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mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd)
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{
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int err;
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struct mmc_command cmd;
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struct mmc_data data;
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int err;
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memset(&cmd, 0, sizeof(cmd));
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memset(&data, 0, sizeof(data));
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@ -1185,9 +1186,9 @@ mmc_send_ext_csd(struct mmc_softc *sc, uint8_t *rawextcsd)
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static int
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mmc_app_sd_status(struct mmc_softc *sc, uint16_t rca, uint32_t *rawsdstatus)
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{
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int err, i;
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struct mmc_command cmd;
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struct mmc_data data;
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int err, i;
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memset(&cmd, 0, sizeof(cmd));
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memset(&data, 0, sizeof(data));
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@ -1393,7 +1394,7 @@ mmc_discover_cards(struct mmc_softc *sc)
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* commands, although the state tables / diagrams in the
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* standard suggest they go back to the transfer state.
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* Other cards don't become deselected, and if we
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* atttempt to blindly re-select them, we get timeout
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* attempt to blindly re-select them, we get timeout
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* errors from some controllers. So we deselect then
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* reselect to handle all situations. The only thing we
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* use from the sd_status is the erase sector size, but
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@ -1534,7 +1535,7 @@ mmc_discover_cards(struct mmc_softc *sc)
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static void
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mmc_rescan_cards(struct mmc_softc *sc)
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{
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struct mmc_ivars *ivar = NULL;
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struct mmc_ivars *ivar;
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device_t *devlist;
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int err, i, devcount;
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@ -1664,14 +1665,13 @@ mmc_go_discovery(struct mmc_softc *sc)
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static int
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mmc_calculate_clock(struct mmc_softc *sc)
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{
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int max_dtr, max_hs_dtr, max_timing;
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int nkid, i, f_max;
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device_t *kids;
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struct mmc_ivars *ivar;
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int i, f_max, max_dtr, max_hs_dtr, max_timing, nkid;
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f_max = mmcbr_get_f_max(sc->dev);
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max_dtr = max_hs_dtr = f_max;
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if ((mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED))
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if (mmcbr_get_caps(sc->dev) & MMC_CAP_HSPEED)
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max_timing = bus_timing_hs;
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else
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max_timing = bus_timing_normal;
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@ -100,7 +100,7 @@ struct mmc_command {
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#define MMC_ERR_FAILED 4
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#define MMC_ERR_INVALID 5
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#define MMC_ERR_NO_MEMORY 6
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#define MMC_ERR_MAX 6
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#define MMC_ERR_MAX 6
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struct mmc_data *data; /* Data segment with cmd */
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struct mmc_request *mrq; /* backpointer to request */
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};
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@ -291,47 +291,47 @@ struct mmc_request {
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/*
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* EXT_CSD fields
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*/
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#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_ERASE_TO_MULT 223 /* RO */
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#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */
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#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */
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#define EXT_CSD_BUS_WIDTH 183 /* R/W */
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#define EXT_CSD_HS_TIMING 185 /* R/W */
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#define EXT_CSD_CARD_TYPE 196 /* RO */
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#define EXT_CSD_REV 192 /* RO */
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#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
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#define EXT_CSD_ERASE_TO_MULT 223 /* RO */
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#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */
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/*
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* EXT_CSD field definitions
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*/
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#define EXT_CSD_CMD_SET_NORMAL 1
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#define EXT_CSD_CMD_SET_SECURE 2
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#define EXT_CSD_CMD_SET_CPSECURE 4
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#define EXT_CSD_CMD_SET_NORMAL 1
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#define EXT_CSD_CMD_SET_SECURE 2
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#define EXT_CSD_CMD_SET_CPSECURE 4
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#define EXT_CSD_CARD_TYPE_26 1
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#define EXT_CSD_CARD_TYPE_52 2
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#define EXT_CSD_CARD_TYPE_26 1
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#define EXT_CSD_CARD_TYPE_52 2
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#define EXT_CSD_BUS_WIDTH_1 0
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#define EXT_CSD_BUS_WIDTH_4 1
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#define EXT_CSD_BUS_WIDTH_8 2
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#define EXT_CSD_BUS_WIDTH_1 0
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#define EXT_CSD_BUS_WIDTH_4 1
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#define EXT_CSD_BUS_WIDTH_8 2
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#define MMC_TYPE_26_MAX_HS 26000000
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#define MMC_TYPE_52_MAX_HS 52000000
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#define MMC_TYPE_26_MAX_HS 26000000
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#define MMC_TYPE_52_MAX_HS 52000000
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/*
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* SD bus widths
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*/
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#define SD_BUS_WIDTH_1 0
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#define SD_BUS_WIDTH_4 2
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#define SD_BUS_WIDTH_1 0
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#define SD_BUS_WIDTH_4 2
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/*
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* SD Switch
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*/
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#define SD_SWITCH_MODE_CHECK 0
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#define SD_SWITCH_MODE_SET 1
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#define SD_SWITCH_GROUP1 0
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#define SD_SWITCH_NORMAL_MODE 0
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#define SD_SWITCH_HS_MODE 1
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#define SD_SWITCH_NOCHANGE 0xF
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#define SD_SWITCH_MODE_CHECK 0
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#define SD_SWITCH_MODE_SET 1
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#define SD_SWITCH_GROUP1 0
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#define SD_SWITCH_NORMAL_MODE 0
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#define SD_SWITCH_HS_MODE 1
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#define SD_SWITCH_NOCHANGE 0xF
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#define SD_CLR_CARD_DETECT 0
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#define SD_SET_CARD_DETECT 1
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@ -419,8 +419,8 @@ struct mmc_scr
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{
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unsigned char sda_vsn;
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unsigned char bus_widths;
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#define SD_SCR_BUS_WIDTH_1 (1<<0)
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#define SD_SCR_BUS_WIDTH_4 (1<<2)
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#define SD_SCR_BUS_WIDTH_1 (1 << 0)
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#define SD_SCR_BUS_WIDTH_4 (1 << 2)
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};
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struct mmc_sd_status
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@ -443,6 +443,6 @@ struct mmc_sd_status
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* byte sector size anywhere, so we assume that such cards are very rare
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* and only note their existence in passing here...
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*/
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#define MMC_SECTOR_SIZE 512
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#define MMC_SECTOR_SIZE 512
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#endif /* DEV_MMCREG_H */
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@ -55,18 +55,19 @@ __FBSDID("$FreeBSD$");
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SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
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static int sdhci_debug;
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SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level");
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SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0,
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"Debug level");
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#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
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#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
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#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
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#define RD_MULTI_4(slot, off, ptr, count) \
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#define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
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#define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
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#define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
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#define RD_MULTI_4(slot, off, ptr, count) \
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SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
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#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
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#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
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#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
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#define WR_MULTI_4(slot, off, ptr, count) \
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#define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
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#define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
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#define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
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#define WR_MULTI_4(slot, off, ptr, count) \
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SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
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static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
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@ -77,13 +78,13 @@ static void sdhci_card_poll(void *);
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static void sdhci_card_task(void *, int);
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/* helper routines */
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#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
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#define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
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#define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
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#define SDHCI_LOCK_INIT(_slot) \
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#define SDHCI_LOCK_INIT(_slot) \
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mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
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#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
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#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
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#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
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#define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
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#define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
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#define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
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#define SDHCI_DEFAULT_MAX_FREQ 50
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@ -97,20 +98,20 @@ static void sdhci_card_task(void *, int);
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* Broadcom BCM577xx Controller Constants
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*/
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/* Maximum divider supported by the default clock source. */
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#define BCM577XX_DEFAULT_MAX_DIVIDER 256
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#define BCM577XX_DEFAULT_MAX_DIVIDER 256
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/* Alternative clock's base frequency. */
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#define BCM577XX_ALT_CLOCK_BASE 63000000
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#define BCM577XX_HOST_CONTROL 0x198
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#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
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#define BCM577XX_CTRL_CLKSEL_SHIFT 12
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#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
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#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
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#define BCM577XX_ALT_CLOCK_BASE 63000000
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#define BCM577XX_HOST_CONTROL 0x198
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#define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF
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#define BCM577XX_CTRL_CLKSEL_SHIFT 12
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#define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0
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#define BCM577XX_CTRL_CLKSEL_64MHZ 0x3
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static void
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sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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if (error != 0) {
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printf("getaddr: error %d\n", error);
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return;
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@ -136,6 +137,7 @@ slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
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static void
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sdhci_dumpregs(struct sdhci_slot *slot)
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{
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slot_printf(slot,
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"============== REGISTER DUMP ==============\n");
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@ -498,9 +500,10 @@ sdhci_transfer_pio(struct sdhci_slot *slot)
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}
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static void
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sdhci_card_task(void *arg, int pending)
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sdhci_card_task(void *arg, int pending __unused)
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{
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struct sdhci_slot *slot = arg;
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device_t d;
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SDHCI_LOCK(slot);
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if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
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@ -519,7 +522,7 @@ sdhci_card_task(void *arg, int pending)
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/* If no card present - detach mmc bus. */
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if (bootverbose || sdhci_debug)
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slot_printf(slot, "Card removed\n");
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device_t d = slot->dev;
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d = slot->dev;
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slot->dev = NULL;
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SDHCI_UNLOCK(slot);
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device_delete_child(slot->bus, d);
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@ -739,6 +742,7 @@ sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
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void
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sdhci_start_slot(struct sdhci_slot *slot)
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{
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sdhci_card_task(slot, 0);
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}
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@ -774,6 +778,7 @@ sdhci_cleanup_slot(struct sdhci_slot *slot)
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int
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sdhci_generic_suspend(struct sdhci_slot *slot)
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{
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sdhci_reset(slot, SDHCI_RESET_ALL);
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return (0);
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@ -782,6 +787,7 @@ sdhci_generic_suspend(struct sdhci_slot *slot)
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int
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sdhci_generic_resume(struct sdhci_slot *slot)
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{
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sdhci_init(slot);
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return (0);
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@ -790,6 +796,7 @@ sdhci_generic_resume(struct sdhci_slot *slot)
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uint32_t
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sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
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{
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if (slot->version >= SDHCI_SPEC_300)
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return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
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else
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@ -869,7 +876,7 @@ sdhci_timeout(void *arg)
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if (slot->curcmd != NULL) {
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slot_printf(slot, " Controller timeout\n");
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sdhci_dumpregs(slot);
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sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
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sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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slot->curcmd->error = MMC_ERR_TIMEOUT;
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sdhci_req_done(slot);
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} else {
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@ -1122,6 +1129,7 @@ void
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sdhci_finish_data(struct sdhci_slot *slot)
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{
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struct mmc_data *data = slot->curcmd->data;
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size_t left;
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/* Interrupt aggregation: Restore command interrupt.
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* Auxiliary restore point for the case when data interrupt
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@ -1133,7 +1141,7 @@ sdhci_finish_data(struct sdhci_slot *slot)
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/* Unload rest of data from DMA buffer. */
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if (!slot->data_done && (slot->flags & SDHCI_USE_DMA)) {
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if (data->flags & MMC_DATA_READ) {
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size_t left = data->len - slot->offset;
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left = data->len - slot->offset;
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bus_dmamap_sync(slot->dmatag, slot->dmamap,
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BUS_DMASYNC_POSTREAD);
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memcpy((u_char*)data->data + slot->offset, slot->dmamem,
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@ -1433,7 +1441,7 @@ sdhci_generic_intr(struct sdhci_slot *slot)
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/* Handle data interrupts. */
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if (intmask & SDHCI_INT_DATA_MASK) {
|
||||
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
|
||||
/* Dont call data_irq in case of errored command */
|
||||
/* Don't call data_irq in case of errored command. */
|
||||
if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0)
|
||||
sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
|
||||
}
|
||||
|
||||
@ -28,246 +28,246 @@
|
||||
#ifndef __SDHCI_H__
|
||||
#define __SDHCI_H__
|
||||
|
||||
#define DMA_BLOCK_SIZE 4096
|
||||
#define DMA_BOUNDARY 0 /* DMA reload every 4K */
|
||||
#define DMA_BLOCK_SIZE 4096
|
||||
#define DMA_BOUNDARY 0 /* DMA reload every 4K */
|
||||
|
||||
/* Controller doesn't honor resets unless we touch the clock register */
|
||||
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
|
||||
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
|
||||
/* Controller really supports DMA */
|
||||
#define SDHCI_QUIRK_FORCE_DMA (1<<1)
|
||||
#define SDHCI_QUIRK_FORCE_DMA (1 << 1)
|
||||
/* Controller has unusable DMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1<<2)
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1 << 2)
|
||||
/* Controller doesn't like to be reset when there is no card inserted. */
|
||||
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<3)
|
||||
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3)
|
||||
/* Controller has flaky internal state so reset it on each ios change */
|
||||
#define SDHCI_QUIRK_RESET_ON_IOS (1<<4)
|
||||
#define SDHCI_QUIRK_RESET_ON_IOS (1 << 4)
|
||||
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<5)
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5)
|
||||
/* Controller needs to be reset after each request to stay stable */
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<6)
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6)
|
||||
/* Controller has an off-by-one issue with timeout value */
|
||||
#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1<<7)
|
||||
#define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7)
|
||||
/* Controller has broken read timings */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMINGS (1<<8)
|
||||
#define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8)
|
||||
/* Controller needs lowered frequency */
|
||||
#define SDHCI_QUIRK_LOWER_FREQUENCY (1<<9)
|
||||
#define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9)
|
||||
/* Data timeout is invalid, should use SD clock */
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<10)
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10)
|
||||
/* Timeout value is invalid, should be overriden */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<11)
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11)
|
||||
/* SDHCI_CAPABILITIES is invalid */
|
||||
#define SDHCI_QUIRK_MISSING_CAPS (1<<12)
|
||||
#define SDHCI_QUIRK_MISSING_CAPS (1 << 12)
|
||||
/* Hardware shifts the 136-bit response, don't do it in software. */
|
||||
#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1<<13)
|
||||
#define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13)
|
||||
/* Wait to see reset bit asserted before waiting for de-asserted */
|
||||
#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1<<14)
|
||||
#define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14)
|
||||
/* Leave controller in standard mode when putting card in HS mode. */
|
||||
#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1<<15)
|
||||
#define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15)
|
||||
/* Alternate clock source is required when supplying a 400 KHz clock. */
|
||||
#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1<<16)
|
||||
#define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16)
|
||||
/* Card insert/remove interrupts don't work, polling required. */
|
||||
#define SDHCI_QUIRK_POLL_CARD_PRESENT (1<<17)
|
||||
#define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17)
|
||||
/* All controller slots are non-removable. */
|
||||
#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1<<18)
|
||||
#define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18)
|
||||
/* Issue custom Intel controller reset sequence after power-up. */
|
||||
#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1<<19)
|
||||
#define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19)
|
||||
/* Data timeout is invalid, use 1 MHz clock instead. */
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1<<20)
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20)
|
||||
|
||||
/*
|
||||
* Controller registers
|
||||
*/
|
||||
#define SDHCI_DMA_ADDRESS 0x00
|
||||
#define SDHCI_DMA_ADDRESS 0x00
|
||||
|
||||
#define SDHCI_BLOCK_SIZE 0x04
|
||||
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
|
||||
#define SDHCI_BLOCK_SIZE 0x04
|
||||
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
|
||||
|
||||
#define SDHCI_BLOCK_COUNT 0x06
|
||||
#define SDHCI_BLOCK_COUNT 0x06
|
||||
|
||||
#define SDHCI_ARGUMENT 0x08
|
||||
#define SDHCI_ARGUMENT 0x08
|
||||
|
||||
#define SDHCI_TRANSFER_MODE 0x0C
|
||||
#define SDHCI_TRNS_DMA 0x01
|
||||
#define SDHCI_TRNS_BLK_CNT_EN 0x02
|
||||
#define SDHCI_TRNS_ACMD12 0x04
|
||||
#define SDHCI_TRNS_READ 0x10
|
||||
#define SDHCI_TRNS_MULTI 0x20
|
||||
#define SDHCI_TRANSFER_MODE 0x0C
|
||||
#define SDHCI_TRNS_DMA 0x01
|
||||
#define SDHCI_TRNS_BLK_CNT_EN 0x02
|
||||
#define SDHCI_TRNS_ACMD12 0x04
|
||||
#define SDHCI_TRNS_READ 0x10
|
||||
#define SDHCI_TRNS_MULTI 0x20
|
||||
|
||||
#define SDHCI_COMMAND_FLAGS 0x0E
|
||||
#define SDHCI_CMD_RESP_NONE 0x00
|
||||
#define SDHCI_CMD_RESP_LONG 0x01
|
||||
#define SDHCI_CMD_RESP_SHORT 0x02
|
||||
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
|
||||
#define SDHCI_CMD_RESP_MASK 0x03
|
||||
#define SDHCI_CMD_CRC 0x08
|
||||
#define SDHCI_CMD_INDEX 0x10
|
||||
#define SDHCI_CMD_DATA 0x20
|
||||
#define SDHCI_CMD_TYPE_NORMAL 0x00
|
||||
#define SDHCI_CMD_TYPE_SUSPEND 0x40
|
||||
#define SDHCI_CMD_TYPE_RESUME 0x80
|
||||
#define SDHCI_CMD_TYPE_ABORT 0xc0
|
||||
#define SDHCI_CMD_TYPE_MASK 0xc0
|
||||
#define SDHCI_COMMAND_FLAGS 0x0E
|
||||
#define SDHCI_CMD_RESP_NONE 0x00
|
||||
#define SDHCI_CMD_RESP_LONG 0x01
|
||||
#define SDHCI_CMD_RESP_SHORT 0x02
|
||||
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
|
||||
#define SDHCI_CMD_RESP_MASK 0x03
|
||||
#define SDHCI_CMD_CRC 0x08
|
||||
#define SDHCI_CMD_INDEX 0x10
|
||||
#define SDHCI_CMD_DATA 0x20
|
||||
#define SDHCI_CMD_TYPE_NORMAL 0x00
|
||||
#define SDHCI_CMD_TYPE_SUSPEND 0x40
|
||||
#define SDHCI_CMD_TYPE_RESUME 0x80
|
||||
#define SDHCI_CMD_TYPE_ABORT 0xc0
|
||||
#define SDHCI_CMD_TYPE_MASK 0xc0
|
||||
|
||||
#define SDHCI_COMMAND 0x0F
|
||||
#define SDHCI_COMMAND 0x0F
|
||||
|
||||
#define SDHCI_RESPONSE 0x10
|
||||
#define SDHCI_RESPONSE 0x10
|
||||
|
||||
#define SDHCI_BUFFER 0x20
|
||||
#define SDHCI_BUFFER 0x20
|
||||
|
||||
#define SDHCI_PRESENT_STATE 0x24
|
||||
#define SDHCI_CMD_INHIBIT 0x00000001
|
||||
#define SDHCI_DAT_INHIBIT 0x00000002
|
||||
#define SDHCI_DAT_ACTIVE 0x00000004
|
||||
#define SDHCI_RETUNE_REQUEST 0x00000008
|
||||
#define SDHCI_DOING_WRITE 0x00000100
|
||||
#define SDHCI_DOING_READ 0x00000200
|
||||
#define SDHCI_SPACE_AVAILABLE 0x00000400
|
||||
#define SDHCI_DATA_AVAILABLE 0x00000800
|
||||
#define SDHCI_CARD_PRESENT 0x00010000
|
||||
#define SDHCI_CARD_STABLE 0x00020000
|
||||
#define SDHCI_CARD_PIN 0x00040000
|
||||
#define SDHCI_WRITE_PROTECT 0x00080000
|
||||
#define SDHCI_STATE_DAT_MASK 0x00f00000
|
||||
#define SDHCI_STATE_CMD 0x01000000
|
||||
#define SDHCI_PRESENT_STATE 0x24
|
||||
#define SDHCI_CMD_INHIBIT 0x00000001
|
||||
#define SDHCI_DAT_INHIBIT 0x00000002
|
||||
#define SDHCI_DAT_ACTIVE 0x00000004
|
||||
#define SDHCI_RETUNE_REQUEST 0x00000008
|
||||
#define SDHCI_DOING_WRITE 0x00000100
|
||||
#define SDHCI_DOING_READ 0x00000200
|
||||
#define SDHCI_SPACE_AVAILABLE 0x00000400
|
||||
#define SDHCI_DATA_AVAILABLE 0x00000800
|
||||
#define SDHCI_CARD_PRESENT 0x00010000
|
||||
#define SDHCI_CARD_STABLE 0x00020000
|
||||
#define SDHCI_CARD_PIN 0x00040000
|
||||
#define SDHCI_WRITE_PROTECT 0x00080000
|
||||
#define SDHCI_STATE_DAT_MASK 0x00f00000
|
||||
#define SDHCI_STATE_CMD 0x01000000
|
||||
|
||||
#define SDHCI_HOST_CONTROL 0x28
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
#define SDHCI_CTRL_HISPD 0x04
|
||||
#define SDHCI_CTRL_SDMA 0x08
|
||||
#define SDHCI_CTRL_ADMA2 0x10
|
||||
#define SDHCI_CTRL_ADMA264 0x18
|
||||
#define SDHCI_CTRL_DMA_MASK 0x18
|
||||
#define SDHCI_CTRL_8BITBUS 0x20
|
||||
#define SDHCI_CTRL_CARD_DET 0x40
|
||||
#define SDHCI_CTRL_FORCE_CARD 0x80
|
||||
#define SDHCI_HOST_CONTROL 0x28
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
#define SDHCI_CTRL_4BITBUS 0x02
|
||||
#define SDHCI_CTRL_HISPD 0x04
|
||||
#define SDHCI_CTRL_SDMA 0x08
|
||||
#define SDHCI_CTRL_ADMA2 0x10
|
||||
#define SDHCI_CTRL_ADMA264 0x18
|
||||
#define SDHCI_CTRL_DMA_MASK 0x18
|
||||
#define SDHCI_CTRL_8BITBUS 0x20
|
||||
#define SDHCI_CTRL_CARD_DET 0x40
|
||||
#define SDHCI_CTRL_FORCE_CARD 0x80
|
||||
|
||||
#define SDHCI_POWER_CONTROL 0x29
|
||||
#define SDHCI_POWER_ON 0x01
|
||||
#define SDHCI_POWER_180 0x0A
|
||||
#define SDHCI_POWER_300 0x0C
|
||||
#define SDHCI_POWER_330 0x0E
|
||||
#define SDHCI_POWER_CONTROL 0x29
|
||||
#define SDHCI_POWER_ON 0x01
|
||||
#define SDHCI_POWER_180 0x0A
|
||||
#define SDHCI_POWER_300 0x0C
|
||||
#define SDHCI_POWER_330 0x0E
|
||||
|
||||
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
|
||||
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
|
||||
|
||||
#define SDHCI_WAKE_UP_CONTROL 0x2B
|
||||
#define SDHCI_WAKE_UP_CONTROL 0x2B
|
||||
|
||||
#define SDHCI_CLOCK_CONTROL 0x2C
|
||||
#define SDHCI_DIVIDER_MASK 0xff
|
||||
#define SDHCI_DIVIDER_MASK_LEN 8
|
||||
#define SDHCI_DIVIDER_SHIFT 8
|
||||
#define SDHCI_DIVIDER_HI_MASK 3
|
||||
#define SDHCI_DIVIDER_HI_SHIFT 6
|
||||
#define SDHCI_CLOCK_CARD_EN 0x0004
|
||||
#define SDHCI_CLOCK_INT_STABLE 0x0002
|
||||
#define SDHCI_CLOCK_INT_EN 0x0001
|
||||
#define SDHCI_DIVIDERS_MASK \
|
||||
#define SDHCI_CLOCK_CONTROL 0x2C
|
||||
#define SDHCI_DIVIDER_MASK 0xff
|
||||
#define SDHCI_DIVIDER_MASK_LEN 8
|
||||
#define SDHCI_DIVIDER_SHIFT 8
|
||||
#define SDHCI_DIVIDER_HI_MASK 3
|
||||
#define SDHCI_DIVIDER_HI_SHIFT 6
|
||||
#define SDHCI_CLOCK_CARD_EN 0x0004
|
||||
#define SDHCI_CLOCK_INT_STABLE 0x0002
|
||||
#define SDHCI_CLOCK_INT_EN 0x0001
|
||||
#define SDHCI_DIVIDERS_MASK \
|
||||
((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \
|
||||
(SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT))
|
||||
|
||||
#define SDHCI_TIMEOUT_CONTROL 0x2E
|
||||
#define SDHCI_TIMEOUT_CONTROL 0x2E
|
||||
|
||||
#define SDHCI_SOFTWARE_RESET 0x2F
|
||||
#define SDHCI_RESET_ALL 0x01
|
||||
#define SDHCI_RESET_CMD 0x02
|
||||
#define SDHCI_RESET_DATA 0x04
|
||||
#define SDHCI_SOFTWARE_RESET 0x2F
|
||||
#define SDHCI_RESET_ALL 0x01
|
||||
#define SDHCI_RESET_CMD 0x02
|
||||
#define SDHCI_RESET_DATA 0x04
|
||||
|
||||
#define SDHCI_INT_STATUS 0x30
|
||||
#define SDHCI_INT_ENABLE 0x34
|
||||
#define SDHCI_SIGNAL_ENABLE 0x38
|
||||
#define SDHCI_INT_RESPONSE 0x00000001
|
||||
#define SDHCI_INT_DATA_END 0x00000002
|
||||
#define SDHCI_INT_BLOCK_GAP 0x00000004
|
||||
#define SDHCI_INT_DMA_END 0x00000008
|
||||
#define SDHCI_INT_SPACE_AVAIL 0x00000010
|
||||
#define SDHCI_INT_DATA_AVAIL 0x00000020
|
||||
#define SDHCI_INT_CARD_INSERT 0x00000040
|
||||
#define SDHCI_INT_CARD_REMOVE 0x00000080
|
||||
#define SDHCI_INT_CARD_INT 0x00000100
|
||||
#define SDHCI_INT_INT_A 0x00000200
|
||||
#define SDHCI_INT_INT_B 0x00000400
|
||||
#define SDHCI_INT_INT_C 0x00000800
|
||||
#define SDHCI_INT_RETUNE 0x00001000
|
||||
#define SDHCI_INT_ERROR 0x00008000
|
||||
#define SDHCI_INT_TIMEOUT 0x00010000
|
||||
#define SDHCI_INT_CRC 0x00020000
|
||||
#define SDHCI_INT_END_BIT 0x00040000
|
||||
#define SDHCI_INT_INDEX 0x00080000
|
||||
#define SDHCI_INT_DATA_TIMEOUT 0x00100000
|
||||
#define SDHCI_INT_DATA_CRC 0x00200000
|
||||
#define SDHCI_INT_DATA_END_BIT 0x00400000
|
||||
#define SDHCI_INT_BUS_POWER 0x00800000
|
||||
#define SDHCI_INT_ACMD12ERR 0x01000000
|
||||
#define SDHCI_INT_ADMAERR 0x02000000
|
||||
#define SDHCI_INT_TUNEERR 0x04000000
|
||||
#define SDHCI_INT_STATUS 0x30
|
||||
#define SDHCI_INT_ENABLE 0x34
|
||||
#define SDHCI_SIGNAL_ENABLE 0x38
|
||||
#define SDHCI_INT_RESPONSE 0x00000001
|
||||
#define SDHCI_INT_DATA_END 0x00000002
|
||||
#define SDHCI_INT_BLOCK_GAP 0x00000004
|
||||
#define SDHCI_INT_DMA_END 0x00000008
|
||||
#define SDHCI_INT_SPACE_AVAIL 0x00000010
|
||||
#define SDHCI_INT_DATA_AVAIL 0x00000020
|
||||
#define SDHCI_INT_CARD_INSERT 0x00000040
|
||||
#define SDHCI_INT_CARD_REMOVE 0x00000080
|
||||
#define SDHCI_INT_CARD_INT 0x00000100
|
||||
#define SDHCI_INT_INT_A 0x00000200
|
||||
#define SDHCI_INT_INT_B 0x00000400
|
||||
#define SDHCI_INT_INT_C 0x00000800
|
||||
#define SDHCI_INT_RETUNE 0x00001000
|
||||
#define SDHCI_INT_ERROR 0x00008000
|
||||
#define SDHCI_INT_TIMEOUT 0x00010000
|
||||
#define SDHCI_INT_CRC 0x00020000
|
||||
#define SDHCI_INT_END_BIT 0x00040000
|
||||
#define SDHCI_INT_INDEX 0x00080000
|
||||
#define SDHCI_INT_DATA_TIMEOUT 0x00100000
|
||||
#define SDHCI_INT_DATA_CRC 0x00200000
|
||||
#define SDHCI_INT_DATA_END_BIT 0x00400000
|
||||
#define SDHCI_INT_BUS_POWER 0x00800000
|
||||
#define SDHCI_INT_ACMD12ERR 0x01000000
|
||||
#define SDHCI_INT_ADMAERR 0x02000000
|
||||
#define SDHCI_INT_TUNEERR 0x04000000
|
||||
|
||||
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
|
||||
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
|
||||
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
|
||||
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
|
||||
|
||||
#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \
|
||||
#define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \
|
||||
SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
|
||||
|
||||
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
|
||||
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK)
|
||||
|
||||
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
|
||||
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
|
||||
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
|
||||
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
|
||||
SDHCI_INT_DATA_END_BIT)
|
||||
|
||||
#define SDHCI_ACMD12_ERR 0x3C
|
||||
#define SDHCI_HOST_CONTROL2 0x3E
|
||||
#define SDHCI_ACMD12_ERR 0x3C
|
||||
#define SDHCI_HOST_CONTROL2 0x3E
|
||||
|
||||
#define SDHCI_CAPABILITIES 0x40
|
||||
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
|
||||
#define SDHCI_TIMEOUT_CLK_SHIFT 0
|
||||
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
|
||||
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
|
||||
#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
|
||||
#define SDHCI_CLOCK_BASE_SHIFT 8
|
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
||||
#define SDHCI_MAX_BLOCK_SHIFT 16
|
||||
#define SDHCI_CAN_DO_8BITBUS 0x00040000
|
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
||||
#define SDHCI_CAN_DO_HISPD 0x00200000
|
||||
#define SDHCI_CAN_DO_DMA 0x00400000
|
||||
#define SDHCI_CAN_DO_SUSPEND 0x00800000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_DO_64BIT 0x10000000
|
||||
#define SDHCI_CAN_ASYNC_INTR 0x20000000
|
||||
#define SDHCI_CAPABILITIES 0x40
|
||||
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
|
||||
#define SDHCI_TIMEOUT_CLK_SHIFT 0
|
||||
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
|
||||
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
|
||||
#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
|
||||
#define SDHCI_CLOCK_BASE_SHIFT 8
|
||||
#define SDHCI_MAX_BLOCK_MASK 0x00030000
|
||||
#define SDHCI_MAX_BLOCK_SHIFT 16
|
||||
#define SDHCI_CAN_DO_8BITBUS 0x00040000
|
||||
#define SDHCI_CAN_DO_ADMA2 0x00080000
|
||||
#define SDHCI_CAN_DO_HISPD 0x00200000
|
||||
#define SDHCI_CAN_DO_DMA 0x00400000
|
||||
#define SDHCI_CAN_DO_SUSPEND 0x00800000
|
||||
#define SDHCI_CAN_VDD_330 0x01000000
|
||||
#define SDHCI_CAN_VDD_300 0x02000000
|
||||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_DO_64BIT 0x10000000
|
||||
#define SDHCI_CAN_ASYNC_INTR 0x20000000
|
||||
|
||||
#define SDHCI_CAPABILITIES2 0x44
|
||||
#define SDHCI_CAN_SDR50 0x00000001
|
||||
#define SDHCI_CAN_SDR104 0x00000002
|
||||
#define SDHCI_CAN_DDR50 0x00000004
|
||||
#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010
|
||||
#define SDHCI_CAN_DRIVE_TYPE_B 0x00000020
|
||||
#define SDHCI_CAN_DRIVE_TYPE_C 0x00000040
|
||||
#define SDHCI_RETUNE_CNT_MASK 0x00000F00
|
||||
#define SDHCI_RETUNE_CNT_SHIFT 8
|
||||
#define SDHCI_TUNE_SDR50 0x00002000
|
||||
#define SDHCI_RETUNE_MODES_MASK 0x0000C000
|
||||
#define SDHCI_RETUNE_MODES_SHIFT 14
|
||||
#define SDHCI_CLOCK_MULT_MASK 0x00FF0000
|
||||
#define SDHCI_CLOCK_MULT_SHIFT 16
|
||||
#define SDHCI_CAPABILITIES2 0x44
|
||||
#define SDHCI_CAN_SDR50 0x00000001
|
||||
#define SDHCI_CAN_SDR104 0x00000002
|
||||
#define SDHCI_CAN_DDR50 0x00000004
|
||||
#define SDHCI_CAN_DRIVE_TYPE_A 0x00000010
|
||||
#define SDHCI_CAN_DRIVE_TYPE_B 0x00000020
|
||||
#define SDHCI_CAN_DRIVE_TYPE_C 0x00000040
|
||||
#define SDHCI_RETUNE_CNT_MASK 0x00000F00
|
||||
#define SDHCI_RETUNE_CNT_SHIFT 8
|
||||
#define SDHCI_TUNE_SDR50 0x00002000
|
||||
#define SDHCI_RETUNE_MODES_MASK 0x0000C000
|
||||
#define SDHCI_RETUNE_MODES_SHIFT 14
|
||||
#define SDHCI_CLOCK_MULT_MASK 0x00FF0000
|
||||
#define SDHCI_CLOCK_MULT_SHIFT 16
|
||||
|
||||
#define SDHCI_MAX_CURRENT 0x48
|
||||
#define SDHCI_FORCE_AUTO_EVENT 0x50
|
||||
#define SDHCI_FORCE_INTR_EVENT 0x52
|
||||
#define SDHCI_ADMA_ERR 0x54
|
||||
#define SDHCI_ADMA_ADDRESS_LOW 0x58
|
||||
#define SDHCI_ADMA_ADDRESS_HI 0x5C
|
||||
#define SDHCI_PRESET_VALUE 0x60
|
||||
#define SDHCI_SHARED_BUS_CTRL 0xE0
|
||||
#define SDHCI_MAX_CURRENT 0x48
|
||||
#define SDHCI_FORCE_AUTO_EVENT 0x50
|
||||
#define SDHCI_FORCE_INTR_EVENT 0x52
|
||||
#define SDHCI_ADMA_ERR 0x54
|
||||
#define SDHCI_ADMA_ADDRESS_LOW 0x58
|
||||
#define SDHCI_ADMA_ADDRESS_HI 0x5C
|
||||
#define SDHCI_PRESET_VALUE 0x60
|
||||
#define SDHCI_SHARED_BUS_CTRL 0xE0
|
||||
|
||||
#define SDHCI_SLOT_INT_STATUS 0xFC
|
||||
#define SDHCI_SLOT_INT_STATUS 0xFC
|
||||
|
||||
#define SDHCI_HOST_VERSION 0xFE
|
||||
#define SDHCI_VENDOR_VER_MASK 0xFF00
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
#define SDHCI_HOST_VERSION 0xFE
|
||||
#define SDHCI_VENDOR_VER_MASK 0xFF00
|
||||
#define SDHCI_VENDOR_VER_SHIFT 8
|
||||
#define SDHCI_SPEC_VER_MASK 0x00FF
|
||||
#define SDHCI_SPEC_VER_SHIFT 0
|
||||
#define SDHCI_SPEC_100 0
|
||||
#define SDHCI_SPEC_200 1
|
||||
#define SDHCI_SPEC_300 2
|
||||
@ -310,10 +310,10 @@ struct sdhci_slot {
|
||||
u_char cmd_done; /* CMD command part done flag */
|
||||
u_char data_done; /* DAT command part done flag */
|
||||
u_char flags; /* Request execution flags */
|
||||
#define CMD_STARTED 1
|
||||
#define STOP_STARTED 2
|
||||
#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
|
||||
#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */
|
||||
#define CMD_STARTED 1
|
||||
#define STOP_STARTED 2
|
||||
#define SDHCI_USE_DMA 4 /* Use DMA for this req. */
|
||||
#define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */
|
||||
struct mtx mtx; /* Slot mutex */
|
||||
};
|
||||
|
||||
|
||||
@ -60,7 +60,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include "mmcbr_if.h"
|
||||
#include "sdhci_if.h"
|
||||
|
||||
#define MAX_SLOTS 6
|
||||
#define MAX_SLOTS 6
|
||||
|
||||
struct sdhci_fdt_softc {
|
||||
device_t dev; /* Controller device */
|
||||
@ -68,7 +68,7 @@ struct sdhci_fdt_softc {
|
||||
u_int caps; /* If we override SDHCI_CAPABILITIES */
|
||||
uint32_t max_clk; /* Max possible freq */
|
||||
struct resource *irq_res; /* IRQ resource */
|
||||
void *intrhand; /* Interrupt handle */
|
||||
void *intrhand; /* Interrupt handle */
|
||||
|
||||
int num_slots; /* Number of slots on this controller*/
|
||||
struct sdhci_slot slots[MAX_SLOTS];
|
||||
@ -79,14 +79,16 @@ static uint8_t
|
||||
sdhci_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
return (bus_read_1(sc->mem_res[slot->num], off));
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
||||
uint8_t val)
|
||||
uint8_t val)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_write_1(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
@ -94,14 +96,16 @@ static uint16_t
|
||||
sdhci_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
return (bus_read_2(sc->mem_res[slot->num], off));
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
||||
uint16_t val)
|
||||
uint16_t val)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_write_2(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
@ -109,14 +113,16 @@ static uint32_t
|
||||
sdhci_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
return (bus_read_4(sc->mem_res[slot->num], off));
|
||||
}
|
||||
|
||||
static void
|
||||
sdhci_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
||||
uint32_t val)
|
||||
uint32_t val)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_write_4(sc->mem_res[slot->num], off, val);
|
||||
}
|
||||
|
||||
@ -125,6 +131,7 @@ sdhci_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot,
|
||||
bus_size_t off, uint32_t *data, bus_size_t count)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
|
||||
}
|
||||
|
||||
@ -133,6 +140,7 @@ sdhci_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
|
||||
bus_size_t off, uint32_t *data, bus_size_t count)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
|
||||
}
|
||||
|
||||
@ -142,10 +150,8 @@ sdhci_fdt_intr(void *arg)
|
||||
struct sdhci_fdt_softc *sc = (struct sdhci_fdt_softc *)arg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
sdhci_generic_intr(slot);
|
||||
}
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_generic_intr(&sc->slots[i]);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -187,6 +193,7 @@ static int
|
||||
sdhci_fdt_attach(device_t dev)
|
||||
{
|
||||
struct sdhci_fdt_softc *sc = device_get_softc(dev);
|
||||
struct sdhci_slot *slot;
|
||||
int err, slots, rid, i;
|
||||
|
||||
sc->dev = dev;
|
||||
@ -194,7 +201,7 @@ sdhci_fdt_attach(device_t dev)
|
||||
/* Allocate IRQ. */
|
||||
rid = 0;
|
||||
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
||||
RF_ACTIVE);
|
||||
RF_ACTIVE);
|
||||
if (sc->irq_res == NULL) {
|
||||
device_printf(dev, "Can't allocate IRQ\n");
|
||||
return (ENOMEM);
|
||||
@ -204,15 +211,15 @@ sdhci_fdt_attach(device_t dev)
|
||||
slots = sc->num_slots; /* number of slots determined in probe(). */
|
||||
sc->num_slots = 0;
|
||||
for (i = 0; i < slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[sc->num_slots];
|
||||
slot = &sc->slots[sc->num_slots];
|
||||
|
||||
/* Allocate memory. */
|
||||
rid = 0;
|
||||
sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
&rid, RF_ACTIVE);
|
||||
if (sc->mem_res[i] == NULL) {
|
||||
device_printf(dev, "Can't allocate memory for "
|
||||
"slot %d\n", i);
|
||||
device_printf(dev,
|
||||
"Can't allocate memory for slot %d\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -236,10 +243,8 @@ sdhci_fdt_attach(device_t dev)
|
||||
}
|
||||
|
||||
/* Process cards detection. */
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
sdhci_start_slot(slot);
|
||||
}
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_start_slot(&sc->slots[i]);
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -253,15 +258,12 @@ sdhci_fdt_detach(device_t dev)
|
||||
bus_generic_detach(dev);
|
||||
bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
|
||||
bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
|
||||
sc->irq_res);
|
||||
sc->irq_res);
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_cleanup_slot(slot);
|
||||
sdhci_cleanup_slot(&sc->slots[i]);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(sc->mem_res[i]),
|
||||
sc->mem_res[i]);
|
||||
rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -269,20 +271,20 @@ sdhci_fdt_detach(device_t dev)
|
||||
|
||||
static device_method_t sdhci_fdt_methods[] = {
|
||||
/* device_if */
|
||||
DEVMETHOD(device_probe, sdhci_fdt_probe),
|
||||
DEVMETHOD(device_attach, sdhci_fdt_attach),
|
||||
DEVMETHOD(device_detach, sdhci_fdt_detach),
|
||||
DEVMETHOD(device_probe, sdhci_fdt_probe),
|
||||
DEVMETHOD(device_attach, sdhci_fdt_attach),
|
||||
DEVMETHOD(device_detach, sdhci_fdt_detach),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
||||
|
||||
/* mmcbr_if */
|
||||
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
||||
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
||||
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
|
||||
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
||||
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
||||
DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
|
||||
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
||||
DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
|
||||
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
||||
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
||||
|
||||
/* SDHCI registers accessors */
|
||||
DEVMETHOD(sdhci_read_1, sdhci_fdt_read_1),
|
||||
|
||||
@ -58,13 +58,13 @@ __FBSDID("$FreeBSD$");
|
||||
* PCI registers
|
||||
*/
|
||||
|
||||
#define PCI_SDHCI_IFPIO 0x00
|
||||
#define PCI_SDHCI_IFDMA 0x01
|
||||
#define PCI_SDHCI_IFVENDOR 0x02
|
||||
#define PCI_SDHCI_IFPIO 0x00
|
||||
#define PCI_SDHCI_IFDMA 0x01
|
||||
#define PCI_SDHCI_IFVENDOR 0x02
|
||||
|
||||
#define PCI_SLOT_INFO 0x40 /* 8 bits */
|
||||
#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
|
||||
#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
|
||||
#define PCI_SLOT_INFO 0x40 /* 8 bits */
|
||||
#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
|
||||
#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
|
||||
|
||||
/*
|
||||
* RICOH specific PCI registers
|
||||
@ -300,6 +300,7 @@ static int
|
||||
sdhci_pci_attach(device_t dev)
|
||||
{
|
||||
struct sdhci_pci_softc *sc = device_get_softc(dev);
|
||||
struct sdhci_slot *slot;
|
||||
uint32_t model;
|
||||
uint16_t subvendor;
|
||||
int bar, err, rid, slots, i;
|
||||
@ -342,7 +343,7 @@ sdhci_pci_attach(device_t dev)
|
||||
}
|
||||
/* Scan all slots. */
|
||||
for (i = 0; i < slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[sc->num_slots];
|
||||
slot = &sc->slots[sc->num_slots];
|
||||
|
||||
/* Allocate memory. */
|
||||
rid = PCIR_BAR(bar + i);
|
||||
@ -353,7 +354,7 @@ sdhci_pci_attach(device_t dev)
|
||||
"Can't allocate memory for slot %d\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
slot->quirks = sc->quirks;
|
||||
|
||||
if (sdhci_init_slot(dev, slot, i) != 0)
|
||||
@ -369,11 +370,8 @@ sdhci_pci_attach(device_t dev)
|
||||
device_printf(dev, "Can't setup IRQ\n");
|
||||
pci_enable_busmaster(dev);
|
||||
/* Process cards detection. */
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_start_slot(slot);
|
||||
}
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_start_slot(&sc->slots[i]);
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -390,9 +388,7 @@ sdhci_pci_detach(device_t dev)
|
||||
pci_release_msi(dev);
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
|
||||
sdhci_cleanup_slot(slot);
|
||||
sdhci_cleanup_slot(&sc->slots[i]);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY,
|
||||
rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
|
||||
}
|
||||
@ -447,20 +443,18 @@ sdhci_pci_intr(void *arg)
|
||||
struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < sc->num_slots; i++) {
|
||||
struct sdhci_slot *slot = &sc->slots[i];
|
||||
sdhci_generic_intr(slot);
|
||||
}
|
||||
for (i = 0; i < sc->num_slots; i++)
|
||||
sdhci_generic_intr(&sc->slots[i]);
|
||||
}
|
||||
|
||||
static device_method_t sdhci_methods[] = {
|
||||
/* device_if */
|
||||
DEVMETHOD(device_probe, sdhci_pci_probe),
|
||||
DEVMETHOD(device_attach, sdhci_pci_attach),
|
||||
DEVMETHOD(device_detach, sdhci_pci_detach),
|
||||
DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
|
||||
DEVMETHOD(device_suspend, sdhci_pci_suspend),
|
||||
DEVMETHOD(device_resume, sdhci_pci_resume),
|
||||
DEVMETHOD(device_probe, sdhci_pci_probe),
|
||||
DEVMETHOD(device_attach, sdhci_pci_attach),
|
||||
DEVMETHOD(device_detach, sdhci_pci_detach),
|
||||
DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
|
||||
DEVMETHOD(device_suspend, sdhci_pci_suspend),
|
||||
DEVMETHOD(device_resume, sdhci_pci_resume),
|
||||
|
||||
/* Bus interface */
|
||||
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user