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Revert an accedintal commit.

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This commit is contained in:
Andrew Turner 2016-09-30 14:00:23 +00:00
parent 6cd8c11ba5
commit 7efd943a95
1 changed files with 20 additions and 42 deletions
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62
sys/arm/include/cpu-v6.h
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@ -345,18 +345,12 @@ tlb_flush_range_local(vm_offset_t va, vm_size_t size)
/* Broadcasting operations. */ /* Broadcasting operations. */
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
/* Used to detect SMP */
extern int mp_ncpus;
static __inline void static __inline void
tlb_flush_all(void) tlb_flush_all(void)
{ {
dsb(); dsb();
if (mp_ncpus == 1) _CP15_TLBIALLIS();
_CP15_TLBIALL();
else
_CP15_TLBIALLIS();
dsb(); dsb();
} }
@ -365,10 +359,7 @@ tlb_flush_all_ng(void)
{ {
dsb(); dsb();
if (mp_ncpus == 1) _CP15_TLBIASIDIS(CPU_ASID_KERNEL);
_CP15_TLBIASID(CPU_ASID_KERNEL);
else
_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
dsb(); dsb();
} }
@ -379,10 +370,7 @@ tlb_flush(vm_offset_t va)
KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
dsb(); dsb();
if (mp_ncpus == 1) _CP15_TLBIMVAAIS(va);
_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
else
_CP15_TLBIMVAAIS(va);
dsb(); dsb();
} }
@ -396,13 +384,8 @@ tlb_flush_range(vm_offset_t va, vm_size_t size)
size)); size));
dsb(); dsb();
if (mp_ncpus == 1) { for (; va < eva; va += PAGE_SIZE)
for (; va < eva; va += PAGE_SIZE) _CP15_TLBIMVAAIS(va);
_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
} else {
for (; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVAAIS(va);
}
dsb(); dsb();
} }
#else /* SMP */ #else /* SMP */
@ -428,19 +411,17 @@ icache_sync(vm_offset_t va, vm_size_t size)
va &= ~cpuinfo.dcache_line_mask; va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) { for ( ; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
if (mp_ncpus > 1) _CP15_DCCMVAU(va);
_CP15_DCCMVAU(va); #else
else _CP15_DCCMVAC(va);
#endif #endif
_CP15_DCCMVAC(va);
} }
dsb(); dsb();
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
if (mp_ncpus > 1) _CP15_ICIALLUIS();
_CP15_ICIALLUIS(); #else
else _CP15_ICIALLU();
#endif #endif
_CP15_ICIALLU();
dsb(); dsb();
isb(); isb();
} }
@ -450,11 +431,10 @@ static __inline void
icache_inv_all(void) icache_inv_all(void)
{ {
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
if (mp_ncpus > 1) _CP15_ICIALLUIS();
_CP15_ICIALLUIS(); #else
else _CP15_ICIALLU();
#endif #endif
_CP15_ICIALLU();
dsb(); dsb();
isb(); isb();
} }
@ -464,11 +444,10 @@ static __inline void
bpb_inv_all(void) bpb_inv_all(void)
{ {
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
if (mp_ncpus > 1) _CP15_BPIALLIS();
_CP15_BPIALLIS(); #else
else _CP15_BPIALL();
#endif #endif
_CP15_BPIALL();
dsb(); dsb();
isb(); isb();
} }
@ -483,11 +462,10 @@ dcache_wb_pou(vm_offset_t va, vm_size_t size)
va &= ~cpuinfo.dcache_line_mask; va &= ~cpuinfo.dcache_line_mask;
for ( ; va < eva; va += cpuinfo.dcache_line_size) { for ( ; va < eva; va += cpuinfo.dcache_line_size) {
#if __ARM_ARCH >= 7 && defined SMP #if __ARM_ARCH >= 7 && defined SMP
if (mp_ncpus > 1) _CP15_DCCMVAU(va);
_CP15_DCCMVAU(va); #else
else _CP15_DCCMVAC(va);
#endif #endif
_CP15_DCCMVAC(va);
} }
dsb(); dsb();
} }