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Correct a typo in the comment part of r320577, later on copied into

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the commit message; as actually implemented, the intent is to retry
up to 2 ms for controllers to enable bus power.
Noticed by: ian@, rgrimes@

Additional note: Among others, the problem addressed by r320577 is
the APL32 ("Storage Controllers May Not Be Power Gated") erratum.
Hopefully, along with r318282, r320577 works around the remaining
problems seen with Intel Apollo Lake eMMC and SDXC controllers.
This commit is contained in:
Marius Strobl 2017-07-03 20:47:32 +00:00
parent 467b3975a3
commit 8022c8eba3
1 changed files with 1 additions and 1 deletions
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2
sys/dev/sdhci/sdhci.c
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@ -398,7 +398,7 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power)
/* /*
* Turn on VDD1 power. Note that at least some Intel controllers can * Turn on VDD1 power. Note that at least some Intel controllers can
* fail to enable bus power on the first try after transiting from D3 * fail to enable bus power on the first try after transiting from D3
* to D0, so we give them up to 20 ms. * to D0, so we give them up to 2 ms.
*/ */
pwr |= SDHCI_POWER_ON; pwr |= SDHCI_POWER_ON;
for (i = 0; i < 20; i++) { for (i = 0; i < 20; i++) {