- Fixed the conversion to bus_space interface.
- Added PC-98 Cbus devices support. The original patch is submitted by chi@bd.mbn.or.jp (Chiharu Shibata) - Removed old ed driver.
This commit is contained in:
Yoshihiro Takahashi
parent
098c6e8747
commit
82583dd564
@ -68,6 +68,9 @@ dev/ata/atapi-all.c count atapist
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dev/ata/atapi-cd.c optional atapicd
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dev/ata/atapi-fd.c optional atapifd
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dev/ata/atapi-tape.c optional atapist
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dev/ed/if_ed.c optional ed
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dev/ed/if_ed_cbus.c optional ed isa
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dev/ed/if_ed_pccard.c optional ed card
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dev/eisa/eisaconf.c count eisa
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dev/fb/fb.c optional fb
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dev/fb/fb.c optional gdc
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@ -348,7 +351,6 @@ pc98/pc98/atapi.c optional wdc
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pc98/pc98/clock.c standard
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pc98/pc98/diskslice_machdep.c standard
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pc98/pc98/fd.c optional fdc
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pc98/pc98/if_ed.c count ed
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pc98/pc98/isa_dma.c optional isa
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pc98/pc98/mse.c optional mse
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pc98/pc98/npx.c mandatory npx
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1001
sys/dev/ed/if_ed.c
1001
sys/dev/ed/if_ed.c
File diff suppressed because it is too large
Load Diff
111
sys/dev/ed/if_ed98.h
Normal file
111
sys/dev/ed/if_ed98.h
Normal file
@ -0,0 +1,111 @@
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/*
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* Copyright (c) KATO Takenori, 1996. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer as
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* the first lines of this file unmodified.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* PC-9801 specific definitions for DP8390/SMC8216 NICs.
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*/
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#ifndef PC98
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#error Why you include if_ed98.h?
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#endif
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/*
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* Vendor types
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*/
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#define ED_VENDOR_MISC 0xf0 /* others */
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/*
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* Card types.
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*
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* Type Card
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* 0x00 Allied Telesis CenterCom LA-98-T / SMC EtherEZ98.
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* 0x10 ** RESERVED **
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* 0x20 PLANET SMART COM 98 EN-2298 / ELECOM LANEED LD-BDN[123]A.
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* 0x30 MELCO EGY-98 / Contec C-NET(98)E-A/L-A.
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* 0x40 MELCO LGY-98, IND-SP, IND-SS / MACNICA NE2098(XXX).
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* 0x50 ICM DT-ET-25, DT-ET-T5, IF-2766ET, IF-2771ET /
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* D-Link DE-298P{T,CAT}, DE-298{T,TP,CAT}.
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* 0x60 Allied Telesis SIC-98.
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* 0x70 ** RESERVED **
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* 0x80 NEC PC-9801-108.
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* 0x90 IO-DATA LA-98 / NEC PC-9801-77.
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* 0xa0 Contec C-NET(98).
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* 0xb0 Contec C-NET(98)E/L.
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* 0xc0 ** RESERVED **
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* 0xd0 Networld EC/EP-98X.
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* 0xe0 Soliton SB-9801 / Fujikura FN-9801 / Networld EC/EP-98S.
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* 0xf0 NextCom NC5098.
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*/
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#define ED_TYPE98_BASE 0x80
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#define ED_TYPE98_GENERIC 0x80
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#define ED_TYPE98_BDN 0x82
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#define ED_TYPE98_EGY 0x83
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#define ED_TYPE98_LGY 0x84
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#define ED_TYPE98_ICM 0x85
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#define ED_TYPE98_SIC 0x86
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#define ED_TYPE98_108 0x88
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#define ED_TYPE98_LA98 0x89
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#define ED_TYPE98_CNET98 0x8a
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#define ED_TYPE98_CNET98EL 0x8b
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#define ED_TYPE98_NW98X 0x8d
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#define ED_TYPE98_SB98 0x8e
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#define ED_TYPE98_NC5098 0x8f
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#define ED_TYPE98(x) (((x & 0xffff0000) >> 20) | ED_TYPE98_BASE)
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#define ED_TYPE98SUB(x) ((x & 0xf0000) >> 16)
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/*
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* Definitions for C-NET(98) serise
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*/
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/*
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* Initial Register(on board JP1)
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*/
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#define ED_CNET98_INIT 0xaaed /* default */
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#define ED_CNET98_INIT2 0x55ed /* another setting */
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#define ED_CNET98EL_PAGE_OFFSET 0x0000 /* Page offset for NIC access to mem */
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/*
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* Definitions for Soliton SB-9801
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*/
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/*
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* I/O port select register
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*/
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#define ED_SB98_IO_INHIBIT 0x0040 /* XXX - shares printer port! */
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/*
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* Definitions for SMC EtherEZ98(SMC8498BTA)
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*/
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#define ED_EZ98_NIC_OFFSET 0x100 /* I/O base offset to NIC */
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#define ED_EZ98_ASIC_OFFSET 0 /* I/O base offset to ASIC */
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/*
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* XXX - The I/O address range is fragmented in the EtherEZ98;
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* it occupies 16*2 I/O addresses, by the way.
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*/
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#define ED_EZ98_IO_PORTS 16 /* # of i/o addresses used */
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1759
sys/dev/ed/if_ed_cbus.c
Normal file
1759
sys/dev/ed/if_ed_cbus.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -66,6 +66,7 @@ ed_isa_probe(dev)
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device_t dev;
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{
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struct ed_softc *sc = device_get_softc(dev);
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int flags = device_get_flags(dev);
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int error = 0;
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bzero(sc, sizeof(struct ed_softc));
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@ -85,22 +86,22 @@ ed_isa_probe(dev)
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/* Heuristic probes */
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error = ed_probe_WD80x3(dev);
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error = ed_probe_WD80x3(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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error = ed_probe_3Com(dev);
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error = ed_probe_3Com(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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error = ed_probe_Novell(dev);
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error = ed_probe_Novell(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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error = ed_probe_HP_pclanp(dev);
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error = ed_probe_HP_pclanp(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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@ -125,17 +126,18 @@ ed_isa_attach(dev)
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ed_alloc_port(dev, sc->port_rid, sc->port_used);
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if (sc->mem_used)
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ed_alloc_memory(dev, sc->mem_rid, sc->mem_used);
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ed_alloc_irq(dev, sc->irq_rid, 0);
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error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET,
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edintr, sc, &sc->irq_handle);
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if (error) {
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ed_release_resources(dev);
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return (error);
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}
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}
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return ed_attach(sc, device_get_unit(dev), flags);
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}
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}
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static device_method_t ed_isa_methods[] = {
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/* Device interface */
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@ -60,7 +60,7 @@ static int ed_pccard_probe(device_t);
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static int ed_pccard_attach(device_t);
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static int ed_pccard_detach(device_t);
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static void ax88190_geteprom(device_t);
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static void ax88190_geteprom(struct ed_softc *);
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static int ed_pccard_memwrite(device_t dev, off_t offset, u_char byte);
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static int ed_pccard_memread(device_t dev, off_t offset, u_char *buf, int size);
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@ -119,11 +119,9 @@ ed_pccard_detach(device_t dev)
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static int
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ed_pccard_probe(device_t dev)
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{
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int error;
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int flags;
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struct ed_softc *sc = device_get_softc(dev);
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flags = device_get_flags(dev);
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struct ed_softc *sc = device_get_softc(dev);
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int flags = device_get_flags(dev);
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int error;
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if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_AX88190) {
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/* Special setup for AX88190 */
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@ -133,34 +131,40 @@ ed_pccard_probe(device_t dev)
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/* XXX Allocate the port resource during setup. */
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error = ed_alloc_port(dev, 0, ED_NOVELL_IO_PORTS);
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if (error != 0)
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if (error)
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return (error);
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sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
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sc->nic_offset = ED_NOVELL_NIC_OFFSET;
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sc->chip_type = ED_CHIP_TYPE_AX88190;
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/*
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* Check & Set Attribute Memory IOBASE Register
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*/
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ed_pccard_memread(dev,ED_AX88190_IOBASE0,rdbuf,4);
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ed_pccard_memread(dev, ED_AX88190_IOBASE0, rdbuf, 4);
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attr_ioport = rdbuf[2] << 8 | rdbuf[0];
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iobase = rman_get_start(sc->port_res);
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if (attr_ioport != iobase) {
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#if notdef
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printf("AX88190 IOBASE MISMATCH %04x -> %04x Setting\n",attr_ioport,iobase);
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printf("AX88190 IOBASE MISMATCH %04x -> %04x Setting\n", attr_ioport, iobase);
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#endif /* notdef */
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ed_pccard_memwrite(dev,ED_AX88190_IOBASE0,iobase & 0xff);
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ed_pccard_memwrite(dev,ED_AX88190_IOBASE1,(iobase >> 8) & 0xff);
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ed_pccard_memwrite(dev, ED_AX88190_IOBASE0,
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iobase & 0xff);
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ed_pccard_memwrite(dev, ED_AX88190_IOBASE1,
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(iobase >> 8) & 0xff);
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}
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ed_ax88190_geteprom(sc);
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ax88190_geteprom(sc);
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ed_release_resources(dev);
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}
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error = ed_probe_Novell(dev);
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error = ed_probe_Novell(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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error = ed_probe_WD80x3(dev);
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error = ed_probe_WD80x3(dev, 0, flags);
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if (error == 0)
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goto end;
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ed_release_resources(dev);
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@ -207,7 +211,57 @@ ed_pccard_attach(device_t dev)
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error = ed_attach(sc, device_get_unit(dev), flags);
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return (error);
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}
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}
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static void
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ax88190_geteprom(struct ed_softc *sc)
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{
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int prom[16],i;
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u_char tmp;
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struct {
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unsigned char offset, value;
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} pg_seq[] = {
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{ED_P0_CR, ED_CR_RD2|ED_CR_STP}, /* Select Page0 */
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{ED_P0_DCR, 0x01},
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{ED_P0_RBCR0, 0x00}, /* Clear the count regs. */
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{ED_P0_RBCR1, 0x00},
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{ED_P0_IMR, 0x00}, /* Mask completion irq. */
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{ED_P0_ISR, 0xff},
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{ED_P0_RCR, ED_RCR_MON | ED_RCR_INTT}, /* Set To Monitor */
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{ED_P0_TCR, ED_TCR_LB0}, /* loopback mode. */
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{ED_P0_RBCR0, 32},
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{ED_P0_RBCR1, 0x00},
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{ED_P0_RSAR0, 0x00},
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{ED_P0_RSAR1, 0x04},
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{ED_P0_CR ,ED_CR_RD0 | ED_CR_STA},
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};
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/* Reset Card */
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tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
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ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
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DELAY(5000);
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ed_asic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
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DELAY(5000);
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|
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/* Card Settings */
|
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for (i = 0; i < sizeof(pg_seq) / sizeof(pg_seq[0]); i++)
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ed_nic_outb(sc, pg_seq[i].offset, pg_seq[i].value);
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/* Get Data */
|
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for (i = 0; i < 16; i++)
|
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prom[i] = ed_asic_inb(sc, 0);
|
||||
/*
|
||||
for (i = 0; i < 16; i++)
|
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printf("ax88190 eprom [%02d] %02x %02x\n",
|
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i,prom[i] & 0xff,prom[i] >> 8);
|
||||
*/
|
||||
sc->arpcom.ac_enaddr[0] = prom[0] & 0xff;
|
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sc->arpcom.ac_enaddr[1] = prom[0] >> 8;
|
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sc->arpcom.ac_enaddr[2] = prom[1] & 0xff;
|
||||
sc->arpcom.ac_enaddr[3] = prom[1] >> 8;
|
||||
sc->arpcom.ac_enaddr[4] = prom[2] & 0xff;
|
||||
sc->arpcom.ac_enaddr[5] = prom[2] >> 8;
|
||||
}
|
||||
|
||||
/* XXX: Warner-san, any plan to provide access to the attribute memory? */
|
||||
static int
|
||||
|
||||
@ -80,11 +80,11 @@ ed_pci_probe (device_t dev)
|
||||
static int
|
||||
ed_pci_attach(device_t dev)
|
||||
{
|
||||
struct ed_softc *sc = device_get_softc(dev);
|
||||
int flags = 0;
|
||||
int error;
|
||||
struct ed_softc *sc = device_get_softc(dev);
|
||||
int flags = 0;
|
||||
int error;
|
||||
|
||||
error = ed_probe_Novell_generic(dev, PCIR_MAPS, flags);
|
||||
error = ed_probe_Novell(dev, PCIR_MAPS, flags);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
|
||||
@ -48,16 +48,8 @@ struct ed_softc {
|
||||
struct resource* irq_res; /* resource for irq */
|
||||
void* irq_handle; /* handle for irq handler */
|
||||
|
||||
bus_space_tag_t bst; /* Bus Space tag */
|
||||
bus_space_handle_t bsh; /* Bus Space handle */
|
||||
|
||||
#ifdef __alpha__
|
||||
u_int asic_addr; /* ASIC I/O bus address */
|
||||
u_int nic_addr; /* NIC (DS8390) I/O bus address */
|
||||
#else
|
||||
u_short asic_addr; /* ASIC I/O bus address */
|
||||
u_short nic_addr; /* NIC (DS8390) I/O bus address */
|
||||
#endif
|
||||
int nic_offset; /* NIC (DS8390) I/O bus address offset */
|
||||
int asic_offset; /* ASIC I/O bus address offset */
|
||||
|
||||
/*
|
||||
* The following 'proto' variable is part of a work-around for 8013EBT asics
|
||||
@ -74,12 +66,12 @@ struct ed_softc {
|
||||
|
||||
u_short hpp_options; /* flags controlling behaviour of the HP card */
|
||||
u_short hpp_id; /* software revision and other fields */
|
||||
u_long hpp_mem_start; /* Memory-mapped IO register address */
|
||||
caddr_t hpp_mem_start; /* Memory-mapped IO register address */
|
||||
|
||||
u_long mem_start; /* NIC memory start address */
|
||||
u_long mem_end; /* NIC memory end address */
|
||||
caddr_t mem_start; /* NIC memory start address */
|
||||
caddr_t mem_end; /* NIC memory end address */
|
||||
u_int32_t mem_size; /* total NIC memory size */
|
||||
u_long mem_ring; /* start of RX ring-buffer (in NIC mem) */
|
||||
caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */
|
||||
|
||||
u_char mem_shared; /* NIC memory is shared with host */
|
||||
u_char xmit_busy; /* transmitter is busy */
|
||||
@ -96,22 +88,123 @@ struct ed_softc {
|
||||
struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
|
||||
};
|
||||
|
||||
#define ed_nic_inb(sc, port) \
|
||||
bus_space_read_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port))
|
||||
|
||||
#define ed_nic_outb(sc, port, value) \
|
||||
bus_space_write_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port), \
|
||||
(value))
|
||||
|
||||
#define ed_nic_inw(sc, port) \
|
||||
bus_space_read_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port))
|
||||
|
||||
#define ed_nic_outw(sc, port, value) \
|
||||
bus_space_write_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port), \
|
||||
(value))
|
||||
|
||||
#define ed_nic_insb(sc, port, addr, count) \
|
||||
bus_space_read_multi_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (addr), (count))
|
||||
|
||||
#define ed_nic_outsb(sc, port, addr, count) \
|
||||
bus_space_write_multi_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (addr), (count))
|
||||
|
||||
#define ed_nic_insw(sc, port, addr, count) \
|
||||
bus_space_read_multi_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (u_int16_t *)(addr), (count))
|
||||
|
||||
#define ed_nic_outsw(sc, port, addr, count) \
|
||||
bus_space_write_multi_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (u_int16_t *)(addr), (count))
|
||||
|
||||
#define ed_nic_insl(sc, port, addr, count) \
|
||||
bus_space_read_multi_4(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (u_int32_t *)(addr), (count))
|
||||
|
||||
#define ed_nic_outsl(sc, port, addr, count) \
|
||||
bus_space_write_multi_4(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->nic_offset + (port), (u_int32_t *)(addr), (count))
|
||||
|
||||
#define ed_asic_inb(sc, port) \
|
||||
bus_space_read_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port))
|
||||
|
||||
#define ed_asic_outb(sc, port, value) \
|
||||
bus_space_write_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port), \
|
||||
(value))
|
||||
|
||||
#define ed_asic_inw(sc, port) \
|
||||
bus_space_read_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port))
|
||||
|
||||
#define ed_asic_outw(sc, port, value) \
|
||||
bus_space_write_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port), \
|
||||
(value))
|
||||
|
||||
#define ed_asic_insb(sc, port, addr, count) \
|
||||
bus_space_read_multi_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (addr), (count))
|
||||
|
||||
#define ed_asic_outsb(sc, port, addr, count) \
|
||||
bus_space_write_multi_1(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (addr), (count))
|
||||
|
||||
#define ed_asic_insw(sc, port, addr, count) \
|
||||
bus_space_read_multi_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (u_int16_t *)(addr), (count))
|
||||
|
||||
#define ed_asic_outsw(sc, port, addr, count) \
|
||||
bus_space_write_multi_2(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (u_int16_t *)(addr), (count))
|
||||
|
||||
#define ed_asic_insl(sc, port, addr, count) \
|
||||
bus_space_read_multi_4(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (u_int32_t *)(addr), (count))
|
||||
|
||||
#define ed_asic_outsl(sc, port, addr, count) \
|
||||
bus_space_write_multi_4(rman_get_bustag((sc)->port_res), \
|
||||
rman_get_bushandle((sc)->port_res), \
|
||||
(sc)->asic_offset + (port), (u_int32_t *)(addr), (count))
|
||||
|
||||
void ed_release_resources __P((device_t));
|
||||
int ed_alloc_port __P((device_t, int, int));
|
||||
int ed_alloc_memory __P((device_t, int, int));
|
||||
int ed_alloc_irq __P((device_t, int, int));
|
||||
|
||||
int ed_probe_generic8390 __P((struct ed_softc *));
|
||||
int ed_probe_WD80x3 __P((device_t));
|
||||
int ed_probe_3Com __P((device_t));
|
||||
int ed_probe_Novell __P((device_t));
|
||||
int ed_probe_Novell_generic __P((device_t, int, int));
|
||||
int ed_probe_HP_pclanp __P((device_t));
|
||||
int ed_probe_WD80x3 __P((device_t, int, int));
|
||||
int ed_probe_WD80x3_generic __P((device_t, int, unsigned short *[]));
|
||||
int ed_probe_3Com __P((device_t, int, int));
|
||||
int ed_probe_Novell __P((device_t, int, int));
|
||||
int ed_probe_Novell_generic __P((device_t, int));
|
||||
int ed_probe_HP_pclanp __P((device_t, int, int));
|
||||
|
||||
int ed_get_Linksys __P((struct ed_softc *));
|
||||
void ed_ax88190_geteprom __P((struct ed_softc *));
|
||||
|
||||
int ed_attach __P((struct ed_softc *, int, int));
|
||||
void ed_stop __P((struct ed_softc *));
|
||||
void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
|
||||
unsigned short));
|
||||
void ed_pio_writemem __P((struct ed_softc *, char *,
|
||||
unsigned short, unsigned short));
|
||||
|
||||
driver_intr_t edintr;
|
||||
|
||||
|
||||
@ -175,7 +175,7 @@ device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
# ISA Ethernet NICs.
|
||||
|
||||
# DP8390 NIC
|
||||
#device ed 1
|
||||
device ed
|
||||
|
||||
# MB86960A NIC
|
||||
options FE_8BIT_SUPPORT # LAC-98 support
|
||||
|
||||
@ -167,66 +167,96 @@ hint.olpt.0.port="0x040"
|
||||
# ed8: C-NET(98)
|
||||
# ed9: C-NET(98)E/L
|
||||
# ed10: EC/EP-98X
|
||||
# ed11: SIU-98-D
|
||||
# ed11: SB-9801
|
||||
# ed12: NC5098
|
||||
#
|
||||
hint.ed.0.at="isa"
|
||||
hint.ed.0.port="0x00d0"
|
||||
hint.ed.0.irq="6"
|
||||
# EtherEZ98
|
||||
#hint.ed.0.at="isa"
|
||||
#hint.ed.0.port="0x00d0"
|
||||
#hint.ed.0.port="0x10d0"
|
||||
#hint.ed.0.irq="6"
|
||||
# SMC EtherEZ98
|
||||
##hint.ed.0.at="isa"
|
||||
##hint.ed.0.port="0x10d0"
|
||||
##hint.ed.0.irq="6"
|
||||
##hint.ed.0.maddr="0xc8000"
|
||||
#hint.ed.0.maddr="0xc8000"
|
||||
hint.ed.5.at="isa"
|
||||
hint.ed.5.port="0x00d0"
|
||||
hint.ed.5.irq="6"
|
||||
hint.ed.5.maddr="0xd0000"
|
||||
hint.ed.5.msize="16384"
|
||||
hint.ed.5.flags="0x600000"
|
||||
# SIU-98-E
|
||||
#hint.ed.5.at="isa"
|
||||
#hint.ed.5.port="0x00d0"
|
||||
#hint.ed.5.irq="6"
|
||||
#hint.ed.5.maddr="0xd0000"
|
||||
#hint.ed.5.msize="16384"
|
||||
#hint.ed.5.flags="0x600000"
|
||||
#hint.ed.1.at="isa"
|
||||
#hint.ed.1.port="0x00d8"
|
||||
#hint.ed.1.irq="6"
|
||||
#hint.ed.1.flags="0x200000"
|
||||
#hint.ed.3.at="isa"
|
||||
#hint.ed.3.port="0x00d0"
|
||||
#hint.ed.3.irq="6"
|
||||
#hint.ed.3.flags="0x400000"
|
||||
#hint.ed.4.at="isa"
|
||||
#hint.ed.4.port="0x56d0"
|
||||
#hint.ed.4.irq="5"
|
||||
#hint.ed.4.flags="0x500000"
|
||||
#hint.ed.2.at="isa"
|
||||
#hint.ed.2.port="0x00d8"
|
||||
#hint.ed.2.irq="6"
|
||||
#hint.ed.2.flags="0x300000"
|
||||
#hint.ed.5.msize="32768"
|
||||
#hint.ed.5.flags="0x610000"
|
||||
hint.ed.1.at="isa"
|
||||
hint.ed.1.port="0x00d8"
|
||||
hint.ed.1.irq="6"
|
||||
hint.ed.1.flags="0x200000"
|
||||
hint.ed.3.at="isa"
|
||||
hint.ed.3.port="0x00d0"
|
||||
hint.ed.3.irq="6"
|
||||
hint.ed.3.flags="0x400000"
|
||||
hint.ed.4.at="isa"
|
||||
hint.ed.4.port="0x56d0"
|
||||
hint.ed.4.irq="5"
|
||||
hint.ed.4.flags="0x500000"
|
||||
hint.ed.2.at="isa"
|
||||
hint.ed.2.port="0x00d8"
|
||||
hint.ed.2.irq="6"
|
||||
hint.ed.2.flags="0x300000"
|
||||
hint.ed.7.at="isa"
|
||||
hint.ed.7.port="0x00d0"
|
||||
hint.ed.7.irq="6"
|
||||
hint.ed.7.flags="0x900000"
|
||||
# PC-9801-77
|
||||
#hint.ed.7.at="isa"
|
||||
#hint.ed.7.port="0x00d0"
|
||||
#hint.ed.7.irq="6"
|
||||
#hint.ed.7.flags="0x900000"
|
||||
#hint.ed.6.at="isa"
|
||||
#hint.ed.6.port="0x0770"
|
||||
#hint.ed.6.irq="6"
|
||||
#hint.ed.6.flags="0x800000"
|
||||
#hint.ed.7.flags="0x910000"
|
||||
hint.ed.6.at="isa"
|
||||
hint.ed.6.port="0x0770"
|
||||
hint.ed.6.irq="6"
|
||||
hint.ed.6.flags="0x800000"
|
||||
hint.ed.9.at="isa"
|
||||
hint.ed.9.port="0x03d0"
|
||||
hint.ed.9.irq="6"
|
||||
hint.ed.9.flags="0xb00000"
|
||||
# C-NET(98)E/L(0x55ED)
|
||||
#hint.ed.9.at="isa"
|
||||
#hint.ed.9.port="0x03d0"
|
||||
#hint.ed.9.irq="6"
|
||||
#hint.ed.9.flags="0xb00000"
|
||||
#hint.ed.8.at="isa"
|
||||
#hint.ed.8.port="0xa3d0"
|
||||
#hint.ed.8.irq="6"
|
||||
#hint.ed.8.maddr="0xd0000"
|
||||
#hint.ed.8.msize="16384"
|
||||
#hint.ed.8.flags="0xa00000"
|
||||
#hint.ed.9.flags="0xb10000"
|
||||
hint.ed.8.at="isa"
|
||||
hint.ed.8.port="0xa3d0"
|
||||
hint.ed.8.irq="6"
|
||||
hint.ed.8.maddr="0xd0000"
|
||||
hint.ed.8.msize="16384"
|
||||
hint.ed.8.flags="0xa00000"
|
||||
# EN1646
|
||||
#hint.ed.10.at="isa"
|
||||
#hint.ed.10.port="0x00d0"
|
||||
#hint.ed.10.irq="3"
|
||||
#hint.ed.10.flags="0xd10000"
|
||||
#hint.ed.10.flags="0xd00000"
|
||||
hint.ed.10.at="isa"
|
||||
hint.ed.10.port="0x00d0"
|
||||
hint.ed.10.irq="3"
|
||||
hint.ed.10.flags="0xd10000"
|
||||
hint.ed.11.at="isa"
|
||||
hint.ed.11.port="0x00d0"
|
||||
hint.ed.11.irq="3"
|
||||
hint.ed.11.flags="0xe00000"
|
||||
# SN-9801-2
|
||||
#hint.ed.11.at="isa"
|
||||
#hint.ed.11.port="0x00d0"
|
||||
#hint.ed.11.irq="6"
|
||||
#hint.ed.11.maddr="0xd0000"
|
||||
#hint.ed.11.msize="32768"
|
||||
#hint.ed.11.flags="0x610000"
|
||||
#hint.ed.11.irq="3"
|
||||
#hint.ed.11.flags="0xe00001"
|
||||
hint.ed.12.at="isa"
|
||||
hint.ed.12.port="0x20d0"
|
||||
hint.ed.12.irq="3"
|
||||
hint.ed.12.flags="0xf00000"
|
||||
|
||||
# fe0: RE1000/1000Plus/AccessPC N98C+/LAC-98
|
||||
hint.fe.0.at="isa"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,505 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) KATO Takenori, 1996. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer as
|
||||
* the first lines of this file unmodified.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* PC-9801 specific definitions for DP8390/SMC8216 NICs.
|
||||
*/
|
||||
#ifndef __PC98_PC98_IF_ED98_H__
|
||||
#define __PC98_PC98_IF_ED98_H__
|
||||
|
||||
/* PC98 only */
|
||||
#ifndef PC98
|
||||
#error Why you include if_ed98.h?
|
||||
#endif
|
||||
|
||||
static int pc98_set_register __P((struct isa_device *dev, int type));
|
||||
static int pc98_set_register_unit __P((struct ed_softc *sc, int type, int iobase));
|
||||
|
||||
/*
|
||||
* Vendor types
|
||||
*/
|
||||
#define ED_VENDOR_MISC 0xf0 /* others */
|
||||
|
||||
/*
|
||||
* Register offsets
|
||||
*/
|
||||
#undef ED_NOVELL_ASIC_OFFSET
|
||||
#define ED_NOVELL_ASIC_OFFSET sc->edreg.asic_offset
|
||||
|
||||
/*
|
||||
* Remote DMA data register; for reading or writing to the NIC mem
|
||||
* via programmed I/O (offset from ASIC base).
|
||||
*/
|
||||
#undef ED_NOVELL_DATA
|
||||
#define ED_NOVELL_DATA sc->edreg.data
|
||||
|
||||
/*
|
||||
* Reset register; reading from this register causes a board reset.
|
||||
*/
|
||||
#undef ED_NOVELL_RESET
|
||||
#define ED_NOVELL_RESET sc->edreg.reset
|
||||
|
||||
/*
|
||||
* Card types.
|
||||
*
|
||||
* Type Card
|
||||
* 0x00 Allied Telesis CenterCom LA-98-T.
|
||||
* 0x10 NE2000 PCMCIA on old 98Note.
|
||||
* 0x20 PLANET SMART COM 98 EN-2298 / ELECOM LANEED LD-BDN[123]A.
|
||||
* 0x30 MELCO EGY-98 / Contec C-NET(98)E-A/L-A.
|
||||
* 0x40 MELCO LGY-98, IND-SP, IND-SS / MACNICA NE2098(XXX).
|
||||
* 0x50 ICM DT-ET-25, DT-ET-T5, IF-2766ET, IF-2771ET /
|
||||
* D-Link DE-298P{T,CAT}, DE-298{T,TP,CAT}.
|
||||
* 0x60 Allied Telesis SIC-98.
|
||||
* 0x70 ** RESERVED **
|
||||
* 0x80 NEC PC-9801-108.
|
||||
* 0x90 IO-DATA LA-98.
|
||||
* 0xa0 Contec C-NET(98).
|
||||
* 0xb0 Contec C-NET(98)E/L.
|
||||
* 0xc0 ** RESERVED **
|
||||
* 0xd0 Networld EC/EP-98X.
|
||||
*/
|
||||
#define ED_TYPE98_BASE 0x80
|
||||
|
||||
#define ED_TYPE98_GENERIC 0x80
|
||||
#define ED_TYPE98_PCIC98 0x81 /* OLD NOTE PCMCIA */
|
||||
#define ED_TYPE98_BDN 0x82
|
||||
#define ED_TYPE98_EGY 0x83
|
||||
#define ED_TYPE98_LGY 0x84
|
||||
#define ED_TYPE98_ICM 0x85
|
||||
#define ED_TYPE98_SIC 0x86
|
||||
#define ED_TYPE98_108 0x88
|
||||
#define ED_TYPE98_LA98 0x89
|
||||
#define ED_TYPE98_CNET98 0x8a
|
||||
#define ED_TYPE98_CNET98EL 0x8b
|
||||
#define ED_TYPE98_NW98X 0x8d
|
||||
|
||||
#define ED_TYPE98(x) (((x & 0xffff0000) >> 20) | ED_TYPE98_BASE)
|
||||
#define ED_TYPE98SUB(x) ((x & 0xf0000) >> 16)
|
||||
|
||||
|
||||
/*
|
||||
* Page 0 register offsets.
|
||||
*/
|
||||
#undef ED_P0_CR
|
||||
#define ED_P0_CR sc->edreg.port[0x00]
|
||||
|
||||
#undef ED_P0_CLDA0
|
||||
#define ED_P0_CLDA0 sc->edreg.port[0x01]
|
||||
#undef ED_P0_PSTART
|
||||
#define ED_P0_PSTART sc->edreg.port[0x01]
|
||||
|
||||
#undef ED_P0_CLDA1
|
||||
#define ED_P0_CLDA1 sc->edreg.port[0x02]
|
||||
#undef ED_P0_PSTOP
|
||||
#define ED_P0_PSTOP sc->edreg.port[0x02]
|
||||
|
||||
#undef ED_P0_BNRY
|
||||
#define ED_P0_BNRY sc->edreg.port[0x03]
|
||||
|
||||
#undef ED_P0_TSR
|
||||
#define ED_P0_TSR sc->edreg.port[0x04]
|
||||
#undef ED_P0_TPSR
|
||||
#define ED_P0_TPSR sc->edreg.port[0x04]
|
||||
|
||||
#undef ED_P0_NCR
|
||||
#define ED_P0_NCR sc->edreg.port[0x05]
|
||||
#undef ED_P0_TBCR0
|
||||
#define ED_P0_TBCR0 sc->edreg.port[0x05]
|
||||
|
||||
#undef ED_P0_FIFO
|
||||
#define ED_P0_FIFO sc->edreg.port[0x06]
|
||||
#undef ED_P0_TBCR1
|
||||
#define ED_P0_TBCR1 sc->edreg.port[0x06]
|
||||
|
||||
#undef ED_P0_ISR
|
||||
#define ED_P0_ISR sc->edreg.port[0x07]
|
||||
|
||||
#undef ED_P0_CRDA0
|
||||
#define ED_P0_CRDA0 sc->edreg.port[0x08]
|
||||
#undef ED_P0_RSAR0
|
||||
#define ED_P0_RSAR0 sc->edreg.port[0x08]
|
||||
|
||||
#undef ED_P0_CRDA1
|
||||
#define ED_P0_CRDA1 sc->edreg.port[0x09]
|
||||
#undef ED_P0_RSAR1
|
||||
#define ED_P0_RSAR1 sc->edreg.port[0x09]
|
||||
|
||||
#undef ED_P0_RBCR0
|
||||
#define ED_P0_RBCR0 sc->edreg.port[0x0a]
|
||||
|
||||
#undef ED_P0_RBCR1
|
||||
#define ED_P0_RBCR1 sc->edreg.port[0x0b]
|
||||
|
||||
#undef ED_P0_RSR
|
||||
#define ED_P0_RSR sc->edreg.port[0x0c]
|
||||
#undef ED_P0_RCR
|
||||
#define ED_P0_RCR sc->edreg.port[0x0c]
|
||||
|
||||
#undef ED_P0_CNTR0
|
||||
#define ED_P0_CNTR0 sc->edreg.port[0x0d]
|
||||
#undef ED_P0_TCR
|
||||
#define ED_P0_TCR sc->edreg.port[0x0d]
|
||||
|
||||
#undef ED_P0_CNTR1
|
||||
#define ED_P0_CNTR1 sc->edreg.port[0x0e]
|
||||
#undef ED_P0_DCR
|
||||
#define ED_P0_DCR sc->edreg.port[0x0e]
|
||||
|
||||
#undef ED_P0_CNTR2
|
||||
#define ED_P0_CNTR2 sc->edreg.port[0x0f]
|
||||
#undef ED_P0_IMR
|
||||
#define ED_P0_IMR sc->edreg.port[0x0f]
|
||||
|
||||
/*
|
||||
* Page 1 register offsets.
|
||||
*/
|
||||
#undef ED_P1_CR
|
||||
#define ED_P1_CR sc->edreg.port[0x00]
|
||||
#undef ED_P1_PAR0
|
||||
#define ED_P1_PAR0 sc->edreg.port[0x01]
|
||||
#undef ED_P1_PAR1
|
||||
#define ED_P1_PAR1 sc->edreg.port[0x02]
|
||||
#undef ED_P1_PAR2
|
||||
#define ED_P1_PAR2 sc->edreg.port[0x03]
|
||||
#undef ED_P1_PAR3
|
||||
#define ED_P1_PAR3 sc->edreg.port[0x04]
|
||||
#undef ED_P1_PAR4
|
||||
#define ED_P1_PAR4 sc->edreg.port[0x05]
|
||||
#undef ED_P1_PAR5
|
||||
#define ED_P1_PAR5 sc->edreg.port[0x06]
|
||||
#undef ED_P1_PAR
|
||||
#define ED_P1_PAR(i) sc->edreg.port[0x01 + i]
|
||||
#undef ED_P1_CURR
|
||||
#define ED_P1_CURR sc->edreg.port[0x07]
|
||||
#undef ED_P1_MAR0
|
||||
#define ED_P1_MAR0 sc->edreg.port[0x08]
|
||||
#undef ED_P1_MAR1
|
||||
#define ED_P1_MAR1 sc->edreg.port[0x09]
|
||||
#undef ED_P1_MAR2
|
||||
#define ED_P1_MAR2 sc->edreg.port[0x0a]
|
||||
#undef ED_P1_MAR3
|
||||
#define ED_P1_MAR3 sc->edreg.port[0x0b]
|
||||
#undef ED_P1_MAR4
|
||||
#define ED_P1_MAR4 sc->edreg.port[0x0c]
|
||||
#undef ED_P1_MAR5
|
||||
#define ED_P1_MAR5 sc->edreg.port[0x0d]
|
||||
#undef ED_P1_MAR6
|
||||
#define ED_P1_MAR6 sc->edreg.port[0x0e]
|
||||
#undef ED_P1_MAR7
|
||||
#define ED_P1_MAR7 sc->edreg.port[0x0f]
|
||||
#undef ED_P1_MAR
|
||||
#define ED_P1_MAR(i) sc->edreg.port[0x08 + i]
|
||||
|
||||
/*
|
||||
* Page 2 register offsets.
|
||||
*/
|
||||
#undef ED_P2_CR
|
||||
#define ED_P2_CR sc->edreg.port[0x00]
|
||||
#undef ED_P2_PSTART
|
||||
#define ED_P2_PSTART sc->edreg.port[0x01]
|
||||
#undef ED_P2_CLDA0
|
||||
#define ED_P2_CLDA0 sc->edreg.port[0x01]
|
||||
#undef ED_P2_PSTOP
|
||||
#define ED_P2_PSTOP sc->edreg.port[0x02]
|
||||
#undef ED_P2_CLDA1
|
||||
#define ED_P2_CLDA1 sc->edreg.port[0x02]
|
||||
#undef ED_P2_RNPP
|
||||
#define ED_P2_RNPP sc->edreg.port[0x03]
|
||||
#undef ED_P2_TPSR
|
||||
#define ED_P2_TPSR sc->edreg.port[0x04]
|
||||
#undef ED_P2_LNPP
|
||||
#define ED_P2_LNPP sc->edreg.port[0x05]
|
||||
#undef ED_P2_ACU
|
||||
#define ED_P2_ACU sc->edreg.port[0x06]
|
||||
#undef ED_P2_ACL
|
||||
#define ED_P2_ACL sc->edreg.port[0x07]
|
||||
#undef ED_P2_RCR
|
||||
#define ED_P2_RCR sc->edreg.port[0x0c]
|
||||
#undef ED_P2_TCR
|
||||
#define ED_P2_TCR sc->edreg.port[0x0d]
|
||||
#undef ED_P2_DCR
|
||||
#define ED_P2_DCR sc->edreg.port[0x0e]
|
||||
#undef ED_P2_IMR
|
||||
#define ED_P2_IMR sc->edreg.port[0x0f]
|
||||
|
||||
/* PCIC98 support */
|
||||
#define ED_PCIC98_16BIT_ON() outb(0x2a8e, 0x94)
|
||||
#define ED_PCIC98_16BIT_OFF() outb(0x2a8e, 0xb4)
|
||||
|
||||
/*
|
||||
* C-NET(98) & C-NET(98)EL
|
||||
*/
|
||||
/*
|
||||
* NIC Initial Register(on board JP1).
|
||||
*/
|
||||
#define ED_CNET98_INIT 0xaaed
|
||||
#define ED_CNET98_INIT2 0x55ed
|
||||
|
||||
/*
|
||||
* C-NET(98)
|
||||
*/
|
||||
#define ED_CNET98_IO_PORTS 16
|
||||
|
||||
/* offset NIC address */
|
||||
#define ED_CNET98_MAP_REG0L 1 /* MAPPING register0 Low. */
|
||||
#define ED_CNET98_MAP_REG1L 3 /* MAPPING register1 Low. */
|
||||
#define ED_CNET98_MAP_REG2L 5 /* MAPPING register2 Low. */
|
||||
#define ED_CNET98_MAP_REG3L 7 /* MAPPING register3 Low. */
|
||||
#define ED_CNET98_MAP_REG0H 9 /* MAPPING register0 Hi. */
|
||||
#define ED_CNET98_MAP_REG1H 11 /* MAPPING register1 Hi. */
|
||||
#define ED_CNET98_MAP_REG2H 13 /* MAPPING register2 Hi. */
|
||||
#define ED_CNET98_MAP_REG3H 15 /* MAPPING register3 Hi. */
|
||||
#define ED_CNET98_WIN_REG (0x400 + 1) /* Window register. */
|
||||
#define ED_CNET98_INT_LEV (0x400 + 3) /* Init level register. */
|
||||
#define ED_CNET98_INT_REQ (0x400 + 5) /* Init request register. */
|
||||
#define ED_CNET98_INT_MASK (0x400 + 7) /* Init mask register. */
|
||||
#define ED_CNET98_INT_STAT (0x400 + 9) /* Init status register. */
|
||||
#define ED_CNET98_INT_CLR (0x400 + 9) /* Init clear register. */
|
||||
#define ED_CNET98_RESERVE1 (0x400 + 11)
|
||||
#define ED_CNET98_RESERVE2 (0x400 + 13)
|
||||
#define ED_CNET98_RESERVE3 (0x400 + 15)
|
||||
#define ED_CNET98_INT_IRQ3 0x01 /* INT 0 */
|
||||
#define ED_CNET98_INT_IRQ5 0x02 /* INT 1 */
|
||||
#define ED_CNET98_INT_IRQ6 0x04 /* INT 2 */
|
||||
#define ED_CNET98_INT_IRQ9 0x08 /* INT 3 */
|
||||
#define ED_CNET98_INT_IRQ12 0x20 /* INT 5 */
|
||||
#define ED_CNET98_INT_IRQ13 0x40 /* INT 6 */
|
||||
|
||||
|
||||
/* C-NET(98)E/L */
|
||||
#define ED_CNET98EL_NIC_OFFSET 0
|
||||
#define ED_CNET98EL_ASIC_OFFSET 0x400 /* Offset to nic i/o regs. */
|
||||
#define ED_CNET98EL_PAGE_OFFSET 0x0000 /* Page offset for NIC access to mem. */
|
||||
/*
|
||||
* XXX - The I/O address range is fragmented in the CNET98E/L; this is the
|
||||
* number of regs at iobase.
|
||||
*/
|
||||
#define ED_CNET98EL_IO_PORTS 16 /* # of i/o addresses used. */
|
||||
/*
|
||||
* Interrupt Configuration Register (offset from ASIC base).
|
||||
*/
|
||||
#define ED_CNET98EL_ICR 0x02
|
||||
|
||||
#define ED_CNET98EL_ICR_IRQ3 0x01 /* Interrupt request 3 select. */
|
||||
#define ED_CNET98EL_ICR_IRQ5 0x02 /* Interrupt request 5 select. */
|
||||
#define ED_CNET98EL_ICR_IRQ6 0x04 /* Interrupt request 6 select. */
|
||||
#define ED_CNET98EL_ICR_IRQ12 0x20 /* Interrupt request 12 select. */
|
||||
/*
|
||||
* Interrupt Mask Register (offset from ASIC base).
|
||||
*/
|
||||
#define ED_CNET98EL_IMR 0x04
|
||||
/*
|
||||
* Interrupt Status Register (offset from ASIC base).
|
||||
*/
|
||||
#define ED_CNET98EL_ISR 0x05
|
||||
|
||||
/*
|
||||
* Networld EC/EP-98X
|
||||
*/
|
||||
/*
|
||||
* Interrupt Status Register (offset from ASIC base).
|
||||
*/
|
||||
#define ED_NW98X_IRQ 0x1000
|
||||
|
||||
#define ED_NW98X_IRQ3 0x04
|
||||
#define ED_NW98X_IRQ5 0x06
|
||||
#define ED_NW98X_IRQ6 0x08
|
||||
#define ED_NW98X_IRQ12 0x0a
|
||||
#define ED_NW98X_IRQ13 0x02
|
||||
|
||||
/* NE2000, LGY-98, ICM, C-NET(98)E/L */
|
||||
static u_short edp_generic[16] = {
|
||||
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
||||
};
|
||||
|
||||
/* EGY-98 */
|
||||
static u_short edp_egy98[16] = {
|
||||
0, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
|
||||
0x100, 0x102, 0x104, 0x106, 0x108, 0x10a, 0x10c, 0x10e
|
||||
};
|
||||
|
||||
/* SIC-98 */
|
||||
static u_short edp_sic98[16] = {
|
||||
0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0a00, 0x0c00, 0x0e00,
|
||||
0x1000, 0x1200, 0x1400, 0x1600, 0x1800, 0x1a00, 0x1c00, 0x1e00
|
||||
};
|
||||
|
||||
/* IO-DATA LA-98, ELECOM LD-BDN */
|
||||
static u_short edp_la98[16] = {
|
||||
0x0000, 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7000,
|
||||
0x8000, 0x9000, 0xa000, 0xb000, 0xc000, 0xd000, 0xe000, 0xf000
|
||||
};
|
||||
|
||||
/* NEC PC-9801-108 */
|
||||
static u_short edp_nec108[16] = {
|
||||
0x0000, 0x0002, 0x0004, 0x0006, 0x0008, 0x000a, 0x000c, 0x000e,
|
||||
0x1000, 0x1002, 0x1004, 0x1006, 0x1008, 0x100a, 0x100c, 0x100e
|
||||
};
|
||||
|
||||
/* Contec C-NET(98) */
|
||||
static u_short edp_cnet98[16] = {
|
||||
0x0000, 0x0002, 0x0004, 0x0006, 0x0008, 0x000a, 0x000c, 0x000e,
|
||||
0x0400, 0x0402, 0x0404, 0x0406, 0x0408, 0x040a, 0x040c, 0x040e
|
||||
};
|
||||
|
||||
/* Networld EC/EP-98X */
|
||||
static u_short edp_nw98x[16] = {
|
||||
0x0000, 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600, 0x0700,
|
||||
0x0800, 0x0900, 0x0a00, 0x0b00, 0x0c00, 0x0d00, 0x0e00, 0x0f00
|
||||
};
|
||||
|
||||
|
||||
static int
|
||||
pc98_set_register(struct isa_device *dev, int type)
|
||||
{
|
||||
return pc98_set_register_unit(&ed_softc[dev->id_unit], type, dev->id_iobase);
|
||||
}
|
||||
|
||||
static int
|
||||
pc98_set_register_unit(struct ed_softc *sc, int type, int iobase)
|
||||
{
|
||||
int adj;
|
||||
int nports;
|
||||
|
||||
sc->type = type;
|
||||
|
||||
switch (type) {
|
||||
default:
|
||||
case ED_TYPE98_GENERIC:
|
||||
sc->edreg.port = edp_generic;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0010;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x000f;
|
||||
nports = 32;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_LGY:
|
||||
sc->edreg.port = edp_generic;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0200;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x0100;
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_EGY:
|
||||
sc->edreg.port = edp_egy98;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0200;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x0100;
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_ICM:
|
||||
case ED_TYPE98_PCIC98:
|
||||
sc->edreg.port = edp_generic;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0100;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x000f;
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_BDN:
|
||||
sc->edreg.port = edp_la98;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0100;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0xc000;
|
||||
nports = 1;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_SIC:
|
||||
sc->edreg.port = edp_sic98;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x2000;
|
||||
ED_NOVELL_DATA = 0; /* dummy */
|
||||
ED_NOVELL_RESET = 0; /* dummy */
|
||||
nports = 1;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_108:
|
||||
sc->edreg.port = edp_nec108;
|
||||
adj = (iobase & 0xf000) / 2;
|
||||
ED_NOVELL_ASIC_OFFSET = (0x0888 | adj) - iobase;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x0002;
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_LA98:
|
||||
sc->edreg.port = edp_la98;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0100;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0xf000;
|
||||
nports = 1;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_CNET98EL:
|
||||
sc->edreg.port = edp_generic;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0400;
|
||||
ED_NOVELL_DATA = 0x000e;
|
||||
ED_NOVELL_RESET = 0; /* dummy */
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_CNET98:
|
||||
sc->edreg.port = edp_cnet98;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x0400;
|
||||
ED_NOVELL_DATA = 0; /* dummy */
|
||||
ED_NOVELL_RESET = 0; /* dummy */
|
||||
nports = 16;
|
||||
break;
|
||||
|
||||
case ED_TYPE98_NW98X:
|
||||
sc->edreg.port = edp_nw98x;
|
||||
ED_NOVELL_ASIC_OFFSET = 0x1000;
|
||||
ED_NOVELL_DATA = 0x0000;
|
||||
ED_NOVELL_RESET = 0x0f00;
|
||||
nports = 1;
|
||||
break;
|
||||
}
|
||||
return nports;
|
||||
}
|
||||
|
||||
/*
|
||||
* SMC EtherEZ98(SMC8498BTA)
|
||||
*
|
||||
* A sample of kernel conf is as follows.
|
||||
* #device ed0 at isa? port 0x10d0 net irq 6 iomem 0xc8000 vector edintr
|
||||
*/
|
||||
#undef ED_WD_NIC_OFFSET
|
||||
#define ED_WD_NIC_OFFSET 0x100 /* I/O base offset to NIC */
|
||||
#undef ED_WD_ASIC_OFFSET
|
||||
#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
|
||||
/*
|
||||
* XXX - The I/O address range is fragmented in the EtherEZ98;
|
||||
* it occupies 16*2 I/O addresses, by the way.
|
||||
*/
|
||||
#undef ED_WD_IO_PORTS
|
||||
#define ED_WD_IO_PORTS 16 /* # of i/o addresses used */
|
||||
|
||||
#endif /* __PC98_PC98_IF_ED98_H__ */
|
||||
Loading…
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Reference in New Issue
Block a user