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ena: Fix styling issues

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Align code style with FreeBSD style(9) guidelines.

Obtained from: Semihalf
MFC after: 2 weeks
Sponsored by: Amazon, Inc.
This commit is contained in:
Dawid Gorecki 2022-06-10 11:18:11 +02:00 committed by Marcin Wojtas
parent 755e60ca04
commit 82e558eacf
10 changed files with 591 additions and 635 deletions
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593
sys/dev/ena/ena.c
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File diff suppressed because it is too large Load Diff

103
sys/dev/ena/ena.h
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@ -58,37 +58,37 @@
#define ENA_DMA_BIT_MASK(x) ((1ULL << (x)) - 1ULL)
/* 1 for AENQ + ADMIN */
#define ENA_ADMIN_MSIX_VEC 1
#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
#define ENA_ADMIN_MSIX_VEC 1
#define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues))
#define ENA_REG_BAR 0
#define ENA_MEM_BAR 2
#define ENA_REG_BAR 0
#define ENA_MEM_BAR 2
#define ENA_BUS_DMA_SEGS 32
#define ENA_BUS_DMA_SEGS 32
#define ENA_DEFAULT_BUF_RING_SIZE 4096
#define ENA_DEFAULT_BUF_RING_SIZE 4096
#define ENA_DEFAULT_RING_SIZE 1024
#define ENA_MIN_RING_SIZE 256
#define ENA_DEFAULT_RING_SIZE 1024
#define ENA_MIN_RING_SIZE 256
/*
* Refill Rx queue when number of required descriptors is above
* QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET
*/
#define ENA_RX_REFILL_THRESH_DIVIDER 8
#define ENA_RX_REFILL_THRESH_PACKET 256
#define ENA_RX_REFILL_THRESH_DIVIDER 8
#define ENA_RX_REFILL_THRESH_PACKET 256
#define ENA_IRQNAME_SIZE 40
#define ENA_IRQNAME_SIZE 40
#define ENA_PKT_MAX_BUFS 19
#define ENA_PKT_MAX_BUFS 19
#define ENA_RX_RSS_TABLE_LOG_SIZE 7
#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
#define ENA_RX_RSS_TABLE_LOG_SIZE 7
#define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
#define ENA_HASH_KEY_SIZE 40
#define ENA_HASH_KEY_SIZE 40
#define ENA_MAX_FRAME_LEN 10000
#define ENA_MIN_FRAME_LEN 60
#define ENA_MAX_FRAME_LEN 10000
#define ENA_MIN_FRAME_LEN 60
#define ENA_TX_RESUME_THRESH (ENA_PKT_MAX_BUFS + 2)
@ -111,26 +111,26 @@
#define RX_IRQ_INTERVAL 20
#define TX_IRQ_INTERVAL 50
#define ENA_MIN_MTU 128
#define ENA_MIN_MTU 128
#define ENA_TSO_MAXSIZE 65536
#define ENA_TSO_MAXSIZE 65536
#define ENA_MMIO_DISABLE_REG_READ BIT(0)
#define ENA_MMIO_DISABLE_REG_READ BIT(0)
#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
#define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
#define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
#define ENA_IO_TXQ_IDX(q) (2 * (q))
#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
#define ENA_IO_TXQ_IDX(q) (2 * (q))
#define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
#define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2)
#define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
#define ENA_MGMNT_IRQ_IDX 0
#define ENA_IO_IRQ_FIRST_IDX 1
#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
#define ENA_MGMNT_IRQ_IDX 0
#define ENA_IO_IRQ_FIRST_IDX 1
#define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q))
#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
#define ENA_MAX_NO_INTERRUPT_ITERATIONS 3
/*
* ENA device should send keep alive msg every 1 sec.
@ -150,12 +150,12 @@
/*
* Supported PCI vendor and devices IDs
*/
#define PCI_VENDOR_ID_AMAZON 0x1d0f
#define PCI_VENDOR_ID_AMAZON 0x1d0f
#define PCI_DEV_ID_ENA_PF 0x0ec2
#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2
#define PCI_DEV_ID_ENA_VF 0xec20
#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21
#define PCI_DEV_ID_ENA_PF 0x0ec2
#define PCI_DEV_ID_ENA_PF_RSERV0 0x1ec2
#define PCI_DEV_ID_ENA_VF 0xec20
#define PCI_DEV_ID_ENA_VF_RSERV0 0xec21
/*
* Flags indicating current ENA driver state
@ -490,9 +490,9 @@ struct ena_adapter {
enum ena_regs_reset_reason_types reset_reason;
};
#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_LOCK(_ring) mtx_lock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_TRYLOCK(_ring) mtx_trylock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_UNLOCK(_ring) mtx_unlock(&(_ring)->ring_mtx)
#define ENA_RING_MTX_ASSERT(_ring) \
mtx_assert(&(_ring)->ring_mtx, MA_OWNED)
@ -503,11 +503,11 @@ struct ena_adapter {
#define ENA_LOCK_UNLOCK() sx_unlock(&ena_global_lock)
#define ENA_LOCK_ASSERT() sx_assert(&ena_global_lock, SA_XLOCKED)
#define ENA_TIMER_INIT(_adapter) \
#define ENA_TIMER_INIT(_adapter) \
callout_init(&(_adapter)->timer_service, true)
#define ENA_TIMER_DRAIN(_adapter) \
#define ENA_TIMER_DRAIN(_adapter) \
callout_drain(&(_adapter)->timer_service)
#define ENA_TIMER_RESET(_adapter) \
#define ENA_TIMER_RESET(_adapter) \
callout_reset_sbt(&(_adapter)->timer_service, SBT_1S, SBT_1S, \
ena_timer_service, (void*)(_adapter), 0)
@ -516,16 +516,6 @@ struct ena_adapter {
extern struct sx ena_global_lock;
static inline int ena_mbuf_count(struct mbuf *mbuf)
{
int count = 1;
while ((mbuf = mbuf->m_next) != NULL)
++count;
return count;
}
int ena_up(struct ena_adapter *adapter);
void ena_down(struct ena_adapter *adapter);
int ena_restore_device(struct ena_adapter *adapter);
@ -537,6 +527,17 @@ int ena_update_queue_size(struct ena_adapter *adapter, uint32_t new_tx_size,
uint32_t new_rx_size);
int ena_update_io_queue_nb(struct ena_adapter *adapter, uint32_t new_num);
static inline int
ena_mbuf_count(struct mbuf *mbuf)
{
int count = 1;
while ((mbuf = mbuf->m_next) != NULL)
++count;
return count;
}
static inline void
ena_trigger_reset(struct ena_adapter *adapter,
enum ena_regs_reset_reason_types reset_reason)

116
sys/dev/ena/ena_datapath.c
View File

@ -46,21 +46,21 @@ __FBSDID("$FreeBSD$");
* Static functions prototypes
*********************************************************************/
static int ena_tx_cleanup(struct ena_ring *);
static int ena_rx_cleanup(struct ena_ring *);
static int ena_tx_cleanup(struct ena_ring *);
static int ena_rx_cleanup(struct ena_ring *);
static inline int ena_get_tx_req_id(struct ena_ring *tx_ring,
struct ena_com_io_cq *io_cq, uint16_t *req_id);
static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *,
static void ena_rx_hash_mbuf(struct ena_ring *, struct ena_com_rx_ctx *,
struct mbuf *);
static struct mbuf* ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *,
static struct mbuf *ena_rx_mbuf(struct ena_ring *, struct ena_com_rx_buf_info *,
struct ena_com_rx_ctx *, uint16_t *);
static inline void ena_rx_checksum(struct ena_ring *, struct ena_com_rx_ctx *,
struct mbuf *);
static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *, bool);
static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring,
static void ena_tx_csum(struct ena_com_tx_ctx *, struct mbuf *, bool);
static int ena_check_and_collapse_mbuf(struct ena_ring *tx_ring,
struct mbuf **mbuf);
static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **);
static void ena_start_xmit(struct ena_ring *);
static int ena_xmit_mbuf(struct ena_ring *, struct mbuf **);
static void ena_start_xmit(struct ena_ring *);
/*********************************************************************
* Global functions
@ -69,12 +69,12 @@ static void ena_start_xmit(struct ena_ring *);
void
ena_cleanup(void *arg, int pending)
{
struct ena_que *que = arg;
struct ena_que *que = arg;
struct ena_adapter *adapter = que->adapter;
if_t ifp = adapter->ifp;
struct ena_ring *tx_ring;
struct ena_ring *rx_ring;
struct ena_com_io_cq* io_cq;
struct ena_com_io_cq *io_cq;
struct ena_eth_io_intr_reg intr_reg;
int qid, ena_qid;
int txc, rxc, i;
@ -101,13 +101,11 @@ ena_cleanup(void *arg, int pending)
return;
if ((txc != TX_BUDGET) && (rxc != RX_BUDGET))
break;
break;
}
/* Signal that work is done and unmask interrupt */
ena_com_update_intr_reg(&intr_reg,
RX_IRQ_INTERVAL,
TX_IRQ_INTERVAL,
ena_com_update_intr_reg(&intr_reg, RX_IRQ_INTERVAL, TX_IRQ_INTERVAL,
true);
counter_u64_add(tx_ring->tx_stats.unmask_interrupt_num, 1);
ena_com_unmask_intr(io_cq, &intr_reg);
@ -119,8 +117,7 @@ ena_deferred_mq_start(void *arg, int pending)
struct ena_ring *tx_ring = (struct ena_ring *)arg;
struct ifnet *ifp = tx_ring->adapter->ifp;
while (!drbr_empty(ifp, tx_ring->br) &&
tx_ring->running &&
while (!drbr_empty(ifp, tx_ring->br) && tx_ring->running &&
(if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
ENA_RING_MTX_LOCK(tx_ring);
ena_start_xmit(tx_ring);
@ -186,7 +183,7 @@ ena_qflush(if_t ifp)
struct ena_ring *tx_ring = adapter->tx_ring;
int i;
for(i = 0; i < adapter->num_io_queues; ++i, ++tx_ring)
for (i = 0; i < adapter->num_io_queues; ++i, ++tx_ring)
if (!drbr_empty(ifp, tx_ring->br)) {
ENA_RING_MTX_LOCK(tx_ring);
drbr_flush(ifp, tx_ring->br);
@ -245,7 +242,7 @@ static int
ena_tx_cleanup(struct ena_ring *tx_ring)
{
struct ena_adapter *adapter;
struct ena_com_io_cq* io_cq;
struct ena_com_io_cq *io_cq;
uint16_t next_to_clean;
uint16_t req_id;
uint16_t ena_qid;
@ -283,8 +280,7 @@ ena_tx_cleanup(struct ena_ring *tx_ring)
bus_dmamap_sync(adapter->tx_buf_tag, tx_info->dmamap,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(adapter->tx_buf_tag,
tx_info->dmamap);
bus_dmamap_unload(adapter->tx_buf_tag, tx_info->dmamap);
ena_log_io(adapter->pdev, DBG, "tx: q %d mbuf %p completed\n",
tx_ring->qid, mbuf);
@ -332,9 +328,8 @@ ena_tx_cleanup(struct ena_ring *tx_ring)
ENA_TX_RESUME_THRESH);
if (unlikely(!tx_ring->running && above_thresh)) {
ENA_RING_MTX_LOCK(tx_ring);
above_thresh =
ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
ENA_TX_RESUME_THRESH);
above_thresh = ena_com_sq_have_enough_space(
tx_ring->ena_com_io_sq, ENA_TX_RESUME_THRESH);
if (!tx_ring->running && above_thresh) {
tx_ring->running = true;
counter_u64_add(tx_ring->tx_stats.queue_wakeup, 1);
@ -422,7 +417,7 @@ ena_rx_hash_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_ctx *ena_rx_ctx,
* @next_to_clean: ring pointer, will be updated only upon success
*
**/
static struct mbuf*
static struct mbuf *
ena_rx_mbuf(struct ena_ring *rx_ring, struct ena_com_rx_buf_info *ena_bufs,
struct ena_com_rx_ctx *ena_rx_ctx, uint16_t *next_to_clean)
{
@ -569,8 +564,8 @@ ena_rx_cleanup(struct ena_ring *rx_ring)
device_t pdev;
struct mbuf *mbuf;
struct ena_com_rx_ctx ena_rx_ctx;
struct ena_com_io_cq* io_cq;
struct ena_com_io_sq* io_sq;
struct ena_com_io_cq *io_cq;
struct ena_com_io_sq *io_sq;
enum ena_regs_reset_reason_types reset_reason;
if_t ifp;
uint16_t ena_qid;
@ -627,14 +622,14 @@ ena_rx_cleanup(struct ena_ring *rx_ring)
if (unlikely(ena_rx_ctx.descs == 0))
break;
ena_log_io(pdev, DBG, "rx: q %d got packet from ena. "
"descs #: %d l3 proto %d l4 proto %d hash: %x\n",
ena_log_io(pdev, DBG,
"rx: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
/* Receive mbuf from the ring */
mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs,
&ena_rx_ctx, &next_to_clean);
mbuf = ena_rx_mbuf(rx_ring, rx_ring->ena_bufs, &ena_rx_ctx,
&next_to_clean);
bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag,
io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD);
/* Exit if we failed to retrieve a buffer */
@ -642,10 +637,8 @@ ena_rx_cleanup(struct ena_ring *rx_ring)
for (i = 0; i < ena_rx_ctx.descs; ++i) {
rx_ring->free_rx_ids[next_to_clean] =
rx_ring->ena_bufs[i].req_id;
next_to_clean =
ENA_RX_RING_IDX_NEXT(next_to_clean,
rx_ring->ring_size);
next_to_clean = ENA_RX_RING_IDX_NEXT(
next_to_clean, rx_ring->ring_size);
}
break;
}
@ -666,7 +659,7 @@ ena_rx_cleanup(struct ena_ring *rx_ring)
* should be computed by hardware.
*/
do_if_input = 1;
if (((ifp->if_capenable & IFCAP_LRO) != 0) &&
if (((ifp->if_capenable & IFCAP_LRO) != 0) &&
((mbuf->m_pkthdr.csum_flags & CSUM_IP_VALID) != 0) &&
(ena_rx_ctx.l4_proto == ENA_ETH_IO_L4_PROTO_TCP)) {
/*
@ -677,11 +670,11 @@ ena_rx_cleanup(struct ena_ring *rx_ring)
*/
if ((rx_ring->lro.lro_cnt != 0) &&
(tcp_lro_rx(&rx_ring->lro, mbuf, 0) == 0))
do_if_input = 0;
do_if_input = 0;
}
if (do_if_input != 0) {
ena_log_io(pdev, DBG, "calling if_input() with mbuf %p\n",
mbuf);
ena_log_io(pdev, DBG,
"calling if_input() with mbuf %p\n", mbuf);
(*ifp->if_input)(ifp, mbuf);
}
@ -873,8 +866,8 @@ ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info,
* For easier maintaining of the DMA map, map the whole mbuf even if
* the LLQ is used. The descriptors will be filled using the segments.
*/
rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag, tx_info->dmamap, mbuf,
segs, &nsegs, BUS_DMA_NOWAIT);
rc = bus_dmamap_load_mbuf_sg(adapter->tx_buf_tag,
tx_info->dmamap, mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
if (unlikely((rc != 0) || (nsegs == 0))) {
ena_log_io(adapter->pdev, WARN,
"dmamap load failed! err: %d nsegs: %d\n", rc, nsegs);
@ -892,24 +885,27 @@ ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info,
* First check if header fits in the mbuf. If not, copy it to
* separate buffer that will be holding linearized data.
*/
*header_len = min_t(uint32_t, mbuf->m_pkthdr.len, tx_ring->tx_max_header_size);
*header_len = min_t(uint32_t, mbuf->m_pkthdr.len,
tx_ring->tx_max_header_size);
/* If header is in linear space, just point into mbuf's data. */
if (likely(*header_len <= mbuf_head_len)) {
*push_hdr = mbuf->m_data;
/*
* Otherwise, copy whole portion of header from multiple mbufs
* to intermediate buffer.
* Otherwise, copy whole portion of header from multiple
* mbufs to intermediate buffer.
*/
} else {
m_copydata(mbuf, 0, *header_len, tx_ring->push_buf_intermediate_buf);
m_copydata(mbuf, 0, *header_len,
tx_ring->push_buf_intermediate_buf);
*push_hdr = tx_ring->push_buf_intermediate_buf;
counter_u64_add(tx_ring->tx_stats.llq_buffer_copy, 1);
}
ena_log_io(adapter->pdev, DBG, "mbuf: %p ""header_buf->vaddr: %p "
"push_len: %d\n", mbuf, *push_hdr, *header_len);
ena_log_io(adapter->pdev, DBG,
"mbuf: %p header_buf->vaddr: %p push_len: %d\n",
mbuf, *push_hdr, *header_len);
/* If packet is fitted in LLQ header, no need for DMA segments. */
if (mbuf->m_pkthdr.len <= tx_ring->tx_max_header_size) {
@ -917,15 +913,18 @@ ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info,
} else {
offset = tx_ring->tx_max_header_size;
/*
* As Header part is mapped to LLQ header, we can skip it and just
* map the residuum of the mbuf to DMA Segments.
* As Header part is mapped to LLQ header, we can skip
* it and just map the residuum of the mbuf to DMA
* Segments.
*/
while (offset > 0) {
if (offset >= segs[iseg].ds_len) {
offset -= segs[iseg].ds_len;
} else {
ena_buf->paddr = segs[iseg].ds_addr + offset;
ena_buf->len = segs[iseg].ds_len - offset;
ena_buf->paddr = segs[iseg].ds_addr +
offset;
ena_buf->len = segs[iseg].ds_len -
offset;
ena_buf++;
tx_info->num_of_bufs++;
offset = 0;
@ -936,12 +935,12 @@ ena_tx_map_mbuf(struct ena_ring *tx_ring, struct ena_tx_buffer *tx_info,
} else {
*push_hdr = NULL;
/*
* header_len is just a hint for the device. Because FreeBSD is not
* giving us information about packet header length and it is not
* guaranteed that all packet headers will be in the 1st mbuf, setting
* header_len to 0 is making the device ignore this value and resolve
* header on it's own.
*/
* header_len is just a hint for the device. Because FreeBSD is
* not giving us information about packet header length and it
* is not guaranteed that all packet headers will be in the 1st
* mbuf, setting header_len to 0 is making the device ignore
* this value and resolve header on it's own.
*/
*header_len = 0;
}
@ -970,7 +969,7 @@ ena_xmit_mbuf(struct ena_ring *tx_ring, struct mbuf **mbuf)
struct ena_tx_buffer *tx_info;
struct ena_com_tx_ctx ena_tx_ctx;
struct ena_com_dev *ena_dev;
struct ena_com_io_sq* io_sq;
struct ena_com_io_sq *io_sq;
void *push_hdr;
uint16_t next_to_use;
uint16_t req_id;
@ -1139,8 +1138,7 @@ ena_start_xmit(struct ena_ring *tx_ring)
drbr_advance(adapter->ifp, tx_ring->br);
if (unlikely((if_getdrvflags(adapter->ifp) &
IFF_DRV_RUNNING) == 0))
if (unlikely((if_getdrvflags(adapter->ifp) & IFF_DRV_RUNNING) == 0))
return;
tx_ring->acum_pkts++;

12
sys/dev/ena/ena_datapath.h
View File

@ -34,12 +34,12 @@
#ifndef ENA_TXRX_H
#define ENA_TXRX_H
void ena_cleanup(void *arg, int pending);
void ena_qflush(if_t ifp);
int ena_mq_start(if_t ifp, struct mbuf *m);
void ena_deferred_mq_start(void *arg, int pending);
void ena_cleanup(void *arg, int pending);
void ena_qflush(if_t ifp);
int ena_mq_start(if_t ifp, struct mbuf *m);
void ena_deferred_mq_start(void *arg, int pending);
#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP)
#define CSUM6_OFFLOAD (CSUM_IP6_UDP|CSUM_IP6_TCP)
#define CSUM_OFFLOAD (CSUM_IP | CSUM_TCP | CSUM_UDP)
#define CSUM6_OFFLOAD (CSUM_IP6_UDP | CSUM_IP6_TCP)
#endif /* ENA_TXRX_H */

140
sys/dev/ena/ena_netmap.c
View File

@ -58,30 +58,28 @@ static int ena_netmap_txsync(struct netmap_kring *, int);
static int ena_netmap_rxsync(struct netmap_kring *, int);
/* Helper functions */
static int ena_netmap_tx_frames(struct ena_netmap_ctx *);
static int ena_netmap_tx_frame(struct ena_netmap_ctx *);
static int ena_netmap_tx_frames(struct ena_netmap_ctx *);
static int ena_netmap_tx_frame(struct ena_netmap_ctx *);
static inline uint16_t ena_netmap_count_slots(struct ena_netmap_ctx *);
static inline uint16_t ena_netmap_packet_len(struct netmap_slot *, u_int,
uint16_t);
static int ena_netmap_copy_data(struct netmap_adapter *,
struct netmap_slot *, u_int, uint16_t, uint16_t, void *);
static int ena_netmap_map_single_slot(struct netmap_adapter *,
static int ena_netmap_copy_data(struct netmap_adapter *, struct netmap_slot *,
u_int, uint16_t, uint16_t, void *);
static int ena_netmap_map_single_slot(struct netmap_adapter *,
struct netmap_slot *, bus_dma_tag_t, bus_dmamap_t, void **, uint64_t *);
static int ena_netmap_tx_map_slots(struct ena_netmap_ctx *,
static int ena_netmap_tx_map_slots(struct ena_netmap_ctx *,
struct ena_tx_buffer *, void **, uint16_t *, uint16_t *);
static void ena_netmap_unmap_last_socket_chain(struct ena_netmap_ctx *,
static void ena_netmap_unmap_last_socket_chain(struct ena_netmap_ctx *,
struct ena_tx_buffer *);
static void ena_netmap_tx_cleanup(struct ena_netmap_ctx *);
static uint16_t ena_netmap_tx_clean_one(struct ena_netmap_ctx *,
uint16_t);
static void ena_netmap_tx_cleanup(struct ena_netmap_ctx *);
static uint16_t ena_netmap_tx_clean_one(struct ena_netmap_ctx *, uint16_t);
static inline int validate_tx_req_id(struct ena_ring *, uint16_t);
static int ena_netmap_rx_frames(struct ena_netmap_ctx *);
static int ena_netmap_rx_frame(struct ena_netmap_ctx *);
static int ena_netmap_rx_load_desc(struct ena_netmap_ctx *, uint16_t,
int *);
static int ena_netmap_rx_load_desc(struct ena_netmap_ctx *, uint16_t, int *);
static void ena_netmap_rx_cleanup(struct ena_netmap_ctx *);
static void ena_netmap_fill_ctx(struct netmap_kring *,
struct ena_netmap_ctx *, uint16_t);
static void ena_netmap_fill_ctx(struct netmap_kring *, struct ena_netmap_ctx *,
uint16_t);
int
ena_netmap_attach(struct ena_adapter *adapter)
@ -106,8 +104,8 @@ ena_netmap_attach(struct ena_adapter *adapter)
}
int
ena_netmap_alloc_rx_slot(struct ena_adapter *adapter,
struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info)
ena_netmap_alloc_rx_slot(struct ena_adapter *adapter, struct ena_ring *rx_ring,
struct ena_rx_buffer *rx_info)
{
struct netmap_adapter *na = NA(adapter->ifp);
struct netmap_kring *kring;
@ -126,12 +124,14 @@ ena_netmap_alloc_rx_slot(struct ena_adapter *adapter,
nm_i = kring->nr_hwcur;
head = kring->rhead;
ena_log_nm(adapter->pdev, DBG, "nr_hwcur: %d, nr_hwtail: %d, "
"rhead: %d, rcur: %d, rtail: %d\n", kring->nr_hwcur,
kring->nr_hwtail, kring->rhead, kring->rcur, kring->rtail);
ena_log_nm(adapter->pdev, DBG,
"nr_hwcur: %d, nr_hwtail: %d, rhead: %d, rcur: %d, rtail: %d\n",
kring->nr_hwcur, kring->nr_hwtail, kring->rhead, kring->rcur,
kring->rtail);
if ((nm_i == head) && rx_ring->initialized) {
ena_log_nm(adapter->pdev, ERR, "No free slots in netmap ring\n");
ena_log_nm(adapter->pdev, ERR,
"No free slots in netmap ring\n");
return (ENOMEM);
}
@ -169,8 +169,8 @@ ena_netmap_alloc_rx_slot(struct ena_adapter *adapter,
}
void
ena_netmap_free_rx_slot(struct ena_adapter *adapter,
struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info)
ena_netmap_free_rx_slot(struct ena_adapter *adapter, struct ena_ring *rx_ring,
struct ena_rx_buffer *rx_info)
{
struct netmap_adapter *na;
struct netmap_kring *kring;
@ -272,7 +272,7 @@ static int
ena_netmap_reg(struct netmap_adapter *na, int onoff)
{
struct ifnet *ifp = na->ifp;
struct ena_adapter* adapter = ifp->if_softc;
struct ena_adapter *adapter = ifp->if_softc;
device_t pdev = adapter->pdev;
struct netmap_kring *kring;
enum txrx t;
@ -358,13 +358,13 @@ ena_netmap_tx_frames(struct ena_netmap_ctx *ctx)
while (ctx->nm_i != ctx->kring->rhead) {
if ((rc = ena_netmap_tx_frame(ctx)) != 0) {
/*
* When there is no empty space in Tx ring, error is
* still being returned. It should not be passed to the
* netmap, as application knows current ring state from
* netmap ring pointers. Returning error there could
* cause application to exit, but the Tx ring is commonly
* being full.
*/
* When there is no empty space in Tx ring, error is
* still being returned. It should not be passed to the
* netmap, as application knows current ring state from
* netmap ring pointers. Returning error there could
* cause application to exit, but the Tx ring is
* commonly being full.
*/
if (rc == ENA_COM_NO_MEM)
rc = 0;
break;
@ -462,7 +462,7 @@ ena_netmap_tx_frame(struct ena_netmap_ctx *ctx)
for (unsigned int i = 0; i < tx_info->num_of_bufs; i++)
bus_dmamap_sync(adapter->tx_buf_tag,
tx_info->nm_info.map_seg[i], BUS_DMASYNC_PREWRITE);
tx_info->nm_info.map_seg[i], BUS_DMASYNC_PREWRITE);
return (0);
}
@ -604,15 +604,12 @@ ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx,
return (EINVAL);
}
/*
* Otherwise, copy whole portion of header from multiple slots
* to intermediate buffer.
* Otherwise, copy whole portion of header from multiple
* slots to intermediate buffer.
*/
} else {
rc = ena_netmap_copy_data(ctx->na,
ctx->slots,
ctx->nm_i,
ctx->lim,
push_len,
rc = ena_netmap_copy_data(ctx->na, ctx->slots,
ctx->nm_i, ctx->lim, push_len,
tx_ring->push_buf_intermediate_buf);
if (unlikely(rc)) {
ena_log_nm(adapter->pdev, ERR,
@ -631,16 +628,12 @@ ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx,
slot->buf_idx, *push_hdr, push_len);
/*
* If header was in linear memory space, map for the dma rest of the data
* in the first mbuf of the mbuf chain.
*/
* If header was in linear memory space, map for the dma rest of
* the data in the first mbuf of the mbuf chain.
*/
if (slot_head_len > push_len) {
rc = ena_netmap_map_single_slot(ctx->na,
slot,
adapter->tx_buf_tag,
*nm_maps,
&vaddr,
&paddr);
rc = ena_netmap_map_single_slot(ctx->na, slot,
adapter->tx_buf_tag, *nm_maps, &vaddr, &paddr);
if (unlikely(rc != 0)) {
ena_log_nm(adapter->pdev, ERR,
"DMA mapping error\n");
@ -688,11 +681,8 @@ ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx,
* Map the data and then assign it with the
* offsets
*/
rc = ena_netmap_map_single_slot(ctx->na,
slot,
adapter->tx_buf_tag,
*nm_maps,
&vaddr,
rc = ena_netmap_map_single_slot(ctx->na, slot,
adapter->tx_buf_tag, *nm_maps, &vaddr,
&paddr);
if (unlikely(rc != 0)) {
ena_log_nm(adapter->pdev, ERR,
@ -724,12 +714,12 @@ ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx,
} else {
*push_hdr = NULL;
/*
* header_len is just a hint for the device. Because netmap is
* not giving us any information about packet header length and
* it is not guaranteed that all packet headers will be in the
* 1st slot, setting header_len to 0 is making the device ignore
* this value and resolve header on it's own.
*/
* header_len is just a hint for the device. Because netmap is
* not giving us any information about packet header length and
* it is not guaranteed that all packet headers will be in the
* 1st slot, setting header_len to 0 is making the device ignore
* this value and resolve header on it's own.
*/
*header_len = 0;
}
@ -737,15 +727,10 @@ ena_netmap_tx_map_slots(struct ena_netmap_ctx *ctx,
while (remaining_len > 0) {
__builtin_prefetch(&ctx->slots[ctx->nm_i + 1]);
rc = ena_netmap_map_single_slot(ctx->na,
slot,
adapter->tx_buf_tag,
*nm_maps,
&vaddr,
&paddr);
rc = ena_netmap_map_single_slot(ctx->na, slot,
adapter->tx_buf_tag, *nm_maps, &vaddr, &paddr);
if (unlikely(rc != 0)) {
ena_log_nm(adapter->pdev, ERR,
"DMA mapping error\n");
ena_log_nm(adapter->pdev, ERR, "DMA mapping error\n");
goto error_map;
}
nm_maps++;
@ -928,13 +913,13 @@ ena_netmap_rx_frames(struct ena_netmap_ctx *ctx)
ctx->nt = ctx->ring->next_to_clean;
ctx->nm_i = ctx->kring->nr_hwtail;
while((rc = ena_netmap_rx_frame(ctx)) == ENA_NETMAP_MORE_FRAMES) {
while ((rc = ena_netmap_rx_frame(ctx)) == ENA_NETMAP_MORE_FRAMES) {
frames_counter++;
/* In case of multiple frames, it is not an error. */
rc = 0;
if (frames_counter > ENA_MAX_FRAMES) {
ena_log_nm(ctx->adapter->pdev, ERR,
"Driver is stuck in the Rx loop\n");
"Driver is stuck in the Rx loop\n");
break;
}
};
@ -976,11 +961,11 @@ ena_netmap_rx_frame(struct ena_netmap_ctx *ctx)
if (unlikely(ena_rx_ctx.descs == 0))
return (ENA_NETMAP_NO_MORE_FRAMES);
ena_log_nm(ctx->adapter->pdev, DBG,
ena_log_nm(ctx->adapter->pdev, DBG,
"Rx: q %d got packet from ena. descs #:"
" %d l3 proto %d l4 proto %d hash: %x\n", ctx->ring->qid,
ena_rx_ctx.descs, ena_rx_ctx.l3_proto, ena_rx_ctx.l4_proto,
ena_rx_ctx.hash);
" %d l3 proto %d l4 proto %d hash: %x\n",
ctx->ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
for (buf = 0; buf < ena_rx_ctx.descs; buf++)
if ((rc = ena_netmap_rx_load_desc(ctx, buf, &len)) != 0)
@ -997,7 +982,7 @@ ena_netmap_rx_frame(struct ena_netmap_ctx *ctx)
}
bus_dmamap_sync(ctx->io_cq->cdesc_addr.mem_handle.tag,
ctx->io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD);
ctx->io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_PREREAD);
counter_enter();
counter_u64_add_protected(ctx->ring->rx_stats.bytes, len);
@ -1012,7 +997,7 @@ rx_clear_desc:
nm = ctx->nm_i;
/* Remove failed packet from ring */
while(buf--) {
while (buf--) {
ctx->slots[nm].flags = 0;
ctx->slots[nm].len = 0;
nm = nm_prev(nm, ctx->lim);
@ -1046,9 +1031,10 @@ ena_netmap_rx_load_desc(struct ena_netmap_ctx *ctx, uint16_t buf, int *len)
ctx->slots[ctx->nm_i].len = ctx->ring->ena_bufs[buf].len;
*len += ctx->slots[ctx->nm_i].len;
ctx->ring->free_rx_ids[ctx->nt] = req_id;
ena_log_nm(ctx->adapter->pdev, DBG, "rx_info %p, buf_idx %d, paddr %jx, nm: %d\n",
rx_info, ctx->slots[ctx->nm_i].buf_idx,
(uintmax_t)rx_info->ena_buf.paddr, ctx->nm_i);
ena_log_nm(ctx->adapter->pdev, DBG,
"rx_info %p, buf_idx %d, paddr %jx, nm: %d\n", rx_info,
ctx->slots[ctx->nm_i].buf_idx, (uintmax_t)rx_info->ena_buf.paddr,
ctx->nm_i);
ctx->nm_i = nm_next(ctx->nm_i, ctx->lim);
ctx->nt = ENA_RX_RING_IDX_NEXT(ctx->nt, ctx->ring->ring_size);

20
sys/dev/ena/ena_netmap.h
View File

@ -42,19 +42,21 @@
#undef unlikely
#endif /* unlikely */
#include <net/netmap.h>
#include <sys/selinfo.h>
#include <net/netmap.h>
#include <dev/netmap/netmap_kern.h>
int ena_netmap_attach(struct ena_adapter *adapter);
int ena_netmap_alloc_rx_slot(struct ena_adapter *adapter,
int ena_netmap_attach(struct ena_adapter *adapter);
int ena_netmap_alloc_rx_slot(struct ena_adapter *adapter,
struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info);
void ena_netmap_free_rx_slot(struct ena_adapter *adapter,
void ena_netmap_free_rx_slot(struct ena_adapter *adapter,
struct ena_ring *rx_ring, struct ena_rx_buffer *rx_info);
bool ena_rx_ring_in_netmap(struct ena_adapter *adapter, int qid);
bool ena_tx_ring_in_netmap(struct ena_adapter *adapter, int qid);
void ena_netmap_reset_rx_ring(struct ena_adapter *adapter, int qid);
void ena_netmap_reset_tx_ring(struct ena_adapter *adapter, int qid);
void ena_netmap_unload(struct ena_adapter *adapter, bus_dmamap_t map);
bool ena_rx_ring_in_netmap(struct ena_adapter *adapter, int qid);
bool ena_tx_ring_in_netmap(struct ena_adapter *adapter, int qid);
void ena_netmap_reset_rx_ring(struct ena_adapter *adapter, int qid);
void ena_netmap_reset_tx_ring(struct ena_adapter *adapter, int qid);
void ena_netmap_unload(struct ena_adapter *adapter, bus_dmamap_t map);
#endif /* _ENA_NETMAP_H_ */

22
sys/dev/ena/ena_rss.c
View File

@ -49,7 +49,8 @@ ena_rss_key_fill(void *key, size_t size)
static bool key_generated;
static uint8_t default_key[ENA_HASH_KEY_SIZE];
KASSERT(size <= ENA_HASH_KEY_SIZE, ("Requested more bytes than ENA RSS key can hold"));
KASSERT(size <= ENA_HASH_KEY_SIZE,
("Requested more bytes than ENA RSS key can hold"));
if (!key_generated) {
arc4random_buf(default_key, ENA_HASH_KEY_SIZE);
@ -73,7 +74,8 @@ ena_rss_reorder_hash_key(u8 *reordered_key, const u8 *key, size_t key_size)
*reordered_key++ = *key--;
}
int ena_rss_set_hash(struct ena_com_dev *ena_dev, const u8 *key)
int
ena_rss_set_hash(struct ena_com_dev *ena_dev, const u8 *key)
{
enum ena_admin_hash_functions ena_func = ENA_ADMIN_TOEPLITZ;
u8 hw_key[ENA_HASH_KEY_SIZE];
@ -84,7 +86,8 @@ int ena_rss_set_hash(struct ena_com_dev *ena_dev, const u8 *key)
ENA_HASH_KEY_SIZE, 0x0));
}
int ena_rss_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
int
ena_rss_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
{
u8 hw_key[ENA_HASH_KEY_SIZE];
int rc;
@ -135,8 +138,8 @@ ena_rss_init_default(struct ena_adapter *adapter)
rc = ena_rss_set_hash(ena_dev, hash_key);
} else
#endif
rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_TOEPLITZ, NULL,
ENA_HASH_KEY_SIZE, 0x0);
rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_TOEPLITZ,
NULL, ENA_HASH_KEY_SIZE, 0x0);
if (unlikely((rc != 0) && (rc != EOPNOTSUPP))) {
ena_log(dev, ERR, "Cannot fill hash function\n");
goto err_rss_destroy;
@ -218,12 +221,14 @@ ena_rss_init_default_deferred(void *arg)
ena_log(adapter->pdev, WARN,
"WARNING: RSS was not properly initialized,"
" it will affect bandwidth\n");
ENA_FLAG_CLEAR_ATOMIC(ENA_FLAG_RSS_ACTIVE, adapter);
ENA_FLAG_CLEAR_ATOMIC(ENA_FLAG_RSS_ACTIVE,
adapter);
}
}
}
}
SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND, ena_rss_init_default_deferred, NULL);
SYSINIT(ena_rss_init, SI_SUB_KICK_SCHEDULER, SI_ORDER_SECOND,
ena_rss_init_default_deferred, NULL);
int
ena_rss_indir_get(struct ena_adapter *adapter, uint32_t *table)
@ -267,8 +272,7 @@ ena_rss_indir_set(struct ena_adapter *adapter, uint32_t *table)
device_printf(adapter->pdev,
"Writing to indirection table not supported\n");
else if (rc != 0)
device_printf(adapter->pdev,
"Cannot set indirection table\n");
device_printf(adapter->pdev, "Cannot set indirection table\n");
return (rc);
}

18
sys/dev/ena/ena_rss.h
View File

@ -44,7 +44,7 @@
#include "ena.h"
#define ENA_RX_RSS_MSG_RECORD_SZ 8
#define ENA_RX_RSS_MSG_RECORD_SZ 8
struct ena_indir {
uint32_t table[ENA_RX_RSS_TABLE_SIZE];
@ -52,12 +52,12 @@ struct ena_indir {
char sysctl_buf[ENA_RX_RSS_TABLE_SIZE * ENA_RX_RSS_MSG_RECORD_SZ];
};
int ena_rss_set_hash(struct ena_com_dev *ena_dev, const u8 *key);
int ena_rss_get_hash_key(struct ena_com_dev *ena_dev, u8 *key);
int ena_rss_configure(struct ena_adapter *);
int ena_rss_indir_get(struct ena_adapter *adapter, uint32_t *table);
int ena_rss_indir_set(struct ena_adapter *adapter, uint32_t *table);
int ena_rss_indir_init(struct ena_adapter *adapter);
int ena_rss_set_hash(struct ena_com_dev *ena_dev, const u8 *key);
int ena_rss_get_hash_key(struct ena_com_dev *ena_dev, u8 *key);
int ena_rss_configure(struct ena_adapter *);
int ena_rss_indir_get(struct ena_adapter *adapter, uint32_t *table);
int ena_rss_indir_set(struct ena_adapter *adapter, uint32_t *table);
int ena_rss_indir_init(struct ena_adapter *adapter);
static inline void
ena_rss_copy_indir_buf(char *buf, uint32_t *table)
@ -65,8 +65,8 @@ ena_rss_copy_indir_buf(char *buf, uint32_t *table)
int i;
for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; ++i) {
buf += snprintf(buf, ENA_RX_RSS_MSG_RECORD_SZ + 1,
"%s%d:%d", i == 0 ? "" : " ", i, table[i]);
buf += snprintf(buf, ENA_RX_RSS_MSG_RECORD_SZ + 1, "%s%d:%d",
i == 0 ? "" : " ", i, table[i]);
}
}

198
sys/dev/ena/ena_sysctl.c
View File

@ -33,29 +33,29 @@ __FBSDID("$FreeBSD$");
#include "opt_rss.h"
#include "ena_sysctl.h"
#include "ena_rss.h"
#include "ena_sysctl.h"
static void ena_sysctl_add_wd(struct ena_adapter *);
static void ena_sysctl_add_stats(struct ena_adapter *);
static void ena_sysctl_add_eni_metrics(struct ena_adapter *);
static void ena_sysctl_add_tuneables(struct ena_adapter *);
static void ena_sysctl_add_wd(struct ena_adapter *);
static void ena_sysctl_add_stats(struct ena_adapter *);
static void ena_sysctl_add_eni_metrics(struct ena_adapter *);
static void ena_sysctl_add_tuneables(struct ena_adapter *);
/* Kernel option RSS prevents manipulation of key hash and indirection table. */
#ifndef RSS
static void ena_sysctl_add_rss(struct ena_adapter *);
static void ena_sysctl_add_rss(struct ena_adapter *);
#endif
static int ena_sysctl_buf_ring_size(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_rx_queue_size(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_io_queues_nb(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_eni_metrics_interval(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_buf_ring_size(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_rx_queue_size(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_io_queues_nb(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_eni_metrics_interval(SYSCTL_HANDLER_ARGS);
#ifndef RSS
static int ena_sysctl_rss_key(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_rss_indir_table(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_rss_key(SYSCTL_HANDLER_ARGS);
static int ena_sysctl_rss_indir_table(SYSCTL_HANDLER_ARGS);
#endif
/* Limit max ENI sample rate to be an hour. */
#define ENI_METRICS_MAX_SAMPLE_INTERVAL 3600
#define ENA_HASH_KEY_MSG_SIZE (ENA_HASH_KEY_SIZE * 2 + 1)
#define ENA_HASH_KEY_MSG_SIZE (ENA_HASH_KEY_SIZE * 2 + 1)
static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
"ENA driver parameters");
@ -64,8 +64,8 @@ static SYSCTL_NODE(_hw, OID_AUTO, ena, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
* Logging level for changing verbosity of the output
*/
int ena_log_level = ENA_INFO;
SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN,
&ena_log_level, 0, "Logging level indicating verbosity of the logs");
SYSCTL_INT(_hw_ena, OID_AUTO, log_level, CTLFLAG_RWTUN, &ena_log_level, 0,
"Logging level indicating verbosity of the logs");
SYSCTL_CONST_STRING(_hw_ena, OID_AUTO, driver_version, CTLFLAG_RD,
DRV_MODULE_VERSION, "ENA driver version");
@ -125,9 +125,8 @@ ena_sysctl_add_wd(struct ena_adapter *adapter)
child = SYSCTL_CHILDREN(tree);
/* Sysctl calls for Watchdog service */
SYSCTL_ADD_INT(ctx, child, OID_AUTO, "wd_active",
CTLFLAG_RWTUN, &adapter->wd_active, 0,
"Watchdog is active");
SYSCTL_ADD_INT(ctx, child, OID_AUTO, "wd_active", CTLFLAG_RWTUN,
&adapter->wd_active, 0, "Watchdog is active");
SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "keep_alive_timeout",
CTLFLAG_RWTUN, &adapter->keep_alive_timeout,
@ -186,82 +185,68 @@ ena_sysctl_add_stats(struct ena_adapter *adapter)
dev_stats = &adapter->dev_stats;
admin_stats = &adapter->ena_dev->admin_queue.stats;
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "wd_expired",
CTLFLAG_RD, &dev_stats->wd_expired,
"Watchdog expiry count");
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "interface_up",
CTLFLAG_RD, &dev_stats->interface_up,
"Network interface up count");
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "wd_expired", CTLFLAG_RD,
&dev_stats->wd_expired, "Watchdog expiry count");
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "interface_up", CTLFLAG_RD,
&dev_stats->interface_up, "Network interface up count");
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "interface_down",
CTLFLAG_RD, &dev_stats->interface_down,
"Network interface down count");
SYSCTL_ADD_COUNTER_U64(ctx, child, OID_AUTO, "admin_q_pause",
CTLFLAG_RD, &dev_stats->admin_q_pause,
"Admin queue pauses");
CTLFLAG_RD, &dev_stats->admin_q_pause, "Admin queue pauses");
for (i = 0; i < adapter->num_io_queues; ++i, ++tx_ring, ++rx_ring) {
snprintf(namebuf, QUEUE_NAME_LEN, "queue%d", i);
queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO,
namebuf, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Queue Name");
queue_list = SYSCTL_CHILDREN(queue_node);
adapter->que[i].oid = queue_node;
#ifdef RSS
/* Common stats */
SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "cpu",
CTLFLAG_RD, &adapter->que[i].cpu, 0, "CPU affinity");
SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "domain",
CTLFLAG_RD, &adapter->que[i].domain, 0, "NUMA domain");
SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "cpu", CTLFLAG_RD,
&adapter->que[i].cpu, 0, "CPU affinity");
SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "domain", CTLFLAG_RD,
&adapter->que[i].domain, 0, "NUMA domain");
#endif
/* TX specific stats */
tx_node = SYSCTL_ADD_NODE(ctx, queue_list, OID_AUTO,
"tx_ring", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX ring");
tx_node = SYSCTL_ADD_NODE(ctx, queue_list, OID_AUTO, "tx_ring",
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX ring");
tx_list = SYSCTL_CHILDREN(tx_node);
tx_stats = &tx_ring->tx_stats;
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "count",
CTLFLAG_RD, &tx_stats->cnt, "Packets sent");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "bytes",
CTLFLAG_RD, &tx_stats->bytes, "Bytes sent");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"count", CTLFLAG_RD,
&tx_stats->cnt, "Packets sent");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"bytes", CTLFLAG_RD,
&tx_stats->bytes, "Bytes sent");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"prepare_ctx_err", CTLFLAG_RD,
&tx_stats->prepare_ctx_err,
"prepare_ctx_err", CTLFLAG_RD, &tx_stats->prepare_ctx_err,
"TX buffer preparation failures");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"dma_mapping_err", CTLFLAG_RD,
&tx_stats->dma_mapping_err, "DMA mapping failures");
"dma_mapping_err", CTLFLAG_RD, &tx_stats->dma_mapping_err,
"DMA mapping failures");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "doorbells",
CTLFLAG_RD, &tx_stats->doorbells, "Queue doorbells");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"doorbells", CTLFLAG_RD,
&tx_stats->doorbells, "Queue doorbells");
"missing_tx_comp", CTLFLAG_RD, &tx_stats->missing_tx_comp,
"TX completions missed");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "bad_req_id",
CTLFLAG_RD, &tx_stats->bad_req_id, "Bad request id count");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "mbuf_collapses",
CTLFLAG_RD, &tx_stats->collapse, "Mbuf collapse count");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"missing_tx_comp", CTLFLAG_RD,
&tx_stats->missing_tx_comp, "TX completions missed");
"mbuf_collapse_err", CTLFLAG_RD, &tx_stats->collapse_err,
"Mbuf collapse failures");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "queue_wakeups",
CTLFLAG_RD, &tx_stats->queue_wakeup, "Queue wakeups");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO, "queue_stops",
CTLFLAG_RD, &tx_stats->queue_stop, "Queue stops");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"bad_req_id", CTLFLAG_RD,
&tx_stats->bad_req_id, "Bad request id count");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"mbuf_collapses", CTLFLAG_RD,
&tx_stats->collapse,
"Mbuf collapse count");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"mbuf_collapse_err", CTLFLAG_RD,
&tx_stats->collapse_err,
"Mbuf collapse failures");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"queue_wakeups", CTLFLAG_RD,
&tx_stats->queue_wakeup, "Queue wakeups");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"queue_stops", CTLFLAG_RD,
&tx_stats->queue_stop, "Queue stops");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"llq_buffer_copy", CTLFLAG_RD,
&tx_stats->llq_buffer_copy,
"llq_buffer_copy", CTLFLAG_RD, &tx_stats->llq_buffer_copy,
"Header copies for llq transaction");
SYSCTL_ADD_COUNTER_U64(ctx, tx_list, OID_AUTO,
"unmask_interrupt_num", CTLFLAG_RD,
@ -269,45 +254,41 @@ ena_sysctl_add_stats(struct ena_adapter *adapter)
"Unmasked interrupt count");
/* RX specific stats */
rx_node = SYSCTL_ADD_NODE(ctx, queue_list, OID_AUTO,
"rx_ring", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX ring");
rx_node = SYSCTL_ADD_NODE(ctx, queue_list, OID_AUTO, "rx_ring",
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX ring");
rx_list = SYSCTL_CHILDREN(rx_node);
rx_stats = &rx_ring->rx_stats;
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "count",
CTLFLAG_RD, &rx_stats->cnt, "Packets received");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "bytes",
CTLFLAG_RD, &rx_stats->bytes, "Bytes received");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "refil_partial",
CTLFLAG_RD, &rx_stats->refil_partial,
"Partial refilled mbufs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "csum_bad",
CTLFLAG_RD, &rx_stats->csum_bad, "Bad RX checksum");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"count", CTLFLAG_RD,
&rx_stats->cnt, "Packets received");
"mbuf_alloc_fail", CTLFLAG_RD, &rx_stats->mbuf_alloc_fail,
"Failed mbuf allocs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"bytes", CTLFLAG_RD,
&rx_stats->bytes, "Bytes received");
"mjum_alloc_fail", CTLFLAG_RD, &rx_stats->mjum_alloc_fail,
"Failed jumbo mbuf allocs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"refil_partial", CTLFLAG_RD,
&rx_stats->refil_partial, "Partial refilled mbufs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"csum_bad", CTLFLAG_RD,
&rx_stats->csum_bad, "Bad RX checksum");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"mbuf_alloc_fail", CTLFLAG_RD,
&rx_stats->mbuf_alloc_fail, "Failed mbuf allocs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"mjum_alloc_fail", CTLFLAG_RD,
&rx_stats->mjum_alloc_fail, "Failed jumbo mbuf allocs");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"dma_mapping_err", CTLFLAG_RD,
&rx_stats->dma_mapping_err, "DMA mapping errors");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"bad_desc_num", CTLFLAG_RD,
&rx_stats->bad_desc_num, "Bad descriptor count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"bad_req_id", CTLFLAG_RD,
&rx_stats->bad_req_id, "Bad request id count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"empty_rx_ring", CTLFLAG_RD,
&rx_stats->empty_rx_ring, "RX descriptors depletion count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO,
"csum_good", CTLFLAG_RD,
&rx_stats->csum_good, "Valid RX checksum calculations");
"dma_mapping_err", CTLFLAG_RD, &rx_stats->dma_mapping_err,
"DMA mapping errors");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "bad_desc_num",
CTLFLAG_RD, &rx_stats->bad_desc_num,
"Bad descriptor count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "bad_req_id",
CTLFLAG_RD, &rx_stats->bad_req_id, "Bad request id count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "empty_rx_ring",
CTLFLAG_RD, &rx_stats->empty_rx_ring,
"RX descriptors depletion count");
SYSCTL_ADD_COUNTER_U64(ctx, rx_list, OID_AUTO, "csum_good",
CTLFLAG_RD, &rx_stats->csum_good,
"Valid RX checksum calculations");
}
/* Stats read from device */
@ -574,7 +555,7 @@ ena_sysctl_rx_queue_size(SYSCTL_HANDLER_ARGS)
if (error != 0 || req->newptr == NULL)
goto unlock;
if (val < ENA_MIN_RING_SIZE || val > adapter->max_rx_ring_size) {
if (val < ENA_MIN_RING_SIZE || val > adapter->max_rx_ring_size) {
ena_log(adapter->pdev, ERR,
"Requested new Rx queue size (%u) is out of range: [%u, %u]\n",
val, ENA_MIN_RING_SIZE, adapter->max_rx_ring_size);
@ -593,8 +574,8 @@ ena_sysctl_rx_queue_size(SYSCTL_HANDLER_ARGS)
if (val != adapter->requested_rx_ring_size) {
ena_log(adapter->pdev, INFO,
"Requested new Rx queue size: %u. Old size: %u\n",
val, adapter->requested_rx_ring_size);
"Requested new Rx queue size: %u. Old size: %u\n", val,
adapter->requested_rx_ring_size);
error = ena_update_queue_size(adapter,
adapter->requested_tx_ring_size, val);
@ -650,19 +631,21 @@ ena_sysctl_io_queues_nb(SYSCTL_HANDLER_ARGS)
*/
if (tmp > (adapter->msix_vecs - ENA_ADMIN_MSIX_VEC)) {
ena_log(adapter->pdev, ERR,
"Requested number of IO queues is higher than maximum "
"allowed (%u)\n", adapter->msix_vecs - ENA_ADMIN_MSIX_VEC);
"Requested number of IO queues is higher than maximum allowed (%u)\n",
adapter->msix_vecs - ENA_ADMIN_MSIX_VEC);
error = EINVAL;
goto unlock;
}
if (tmp == adapter->num_io_queues) {
ena_log(adapter->pdev, ERR,
"Requested number of IO queues is equal to current value "
"(%u)\n", adapter->num_io_queues);
"(%u)\n",
adapter->num_io_queues);
} else {
ena_log(adapter->pdev, INFO,
"Requested new number of IO queues: %u, current value: "
"%u\n", tmp, adapter->num_io_queues);
"%u\n",
tmp, adapter->num_io_queues);
old_num_queues = adapter->num_io_queues;
error = ena_update_io_queue_nb(adapter, tmp);
@ -713,7 +696,8 @@ ena_sysctl_eni_metrics_interval(SYSCTL_HANDLER_ARGS)
bzero(&adapter->eni_metrics, sizeof(adapter->eni_metrics));
} else {
ena_log(adapter->pdev, INFO,
"ENI metrics update interval is set to: %"PRIu16" seconds\n",
"ENI metrics update interval is set to: %" PRIu16
" seconds\n",
interval);
}

4
sys/dev/ena/ena_sysctl.h
View File

@ -39,8 +39,8 @@
#include "ena.h"
void ena_sysctl_add_nodes(struct ena_adapter *adapter);
void ena_sysctl_update_queue_node_nb(struct ena_adapter *adapter, int old,
void ena_sysctl_add_nodes(struct ena_adapter *adapter);
void ena_sysctl_update_queue_node_nb(struct ena_adapter *adapter, int old,
int new);
extern int ena_enable_9k_mbufs;