Add llvm patch corresponding to r280865.
This commit is contained in:
Dimitry Andric
parent
2f22c84c31
commit
830e9b84d8
@ -0,0 +1,811 @@
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Pull in r231227 from upstream llvm trunk (by Kristof Beyls):
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Fix PR22408 - LLVM producing AArch64 TLS relocations that GNU linkers
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cannot handle yet.
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As is described at http://llvm.org/bugs/show_bug.cgi?id=22408, the
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GNU linkers ld.bfd and ld.gold currently only support a subset of the
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whole range of AArch64 ELF TLS relocations. Furthermore, they assume
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that some of the code sequences to access thread-local variables are
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produced in a very specific sequence. When the sequence is not as the
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linker expects, it can silently mis-relaxe/mis-optimize the
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instructions.
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Even if that wouldn't be the case, it's good to produce the exact
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sequence, as that ensures that linkers can perform optimizing
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relaxations.
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This patch:
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* implements support for 16MiB TLS area size instead of 4GiB TLS area
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size. Ideally clang would grow an -mtls-size option to allow
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support for both, but that's not part of this patch.
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* by default doesn't produce local dynamic access patterns, as even
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modern ld.bfd and ld.gold linkers do not support the associated
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relocations. An option (-aarch64-elf-ldtls-generation) is added to
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enable generation of local dynamic code sequence, but is off by
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default.
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* makes sure that the exact expected code sequence for local dynamic
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and general dynamic accesses is produced, by making use of a new
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pseudo instruction. The patch also removes two
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(AArch64ISD::TLSDESC_BLR, AArch64ISD::TLSDESC_CALL) pre-existing
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AArch64-specific pseudo SDNode instructions that are superseded by
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the new one (TLSDESC_CALLSEQ).
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Introduced here: https://svnweb.freebsd.org/changeset/base/280865
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Index: lib/Target/AArch64/AArch64AsmPrinter.cpp
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===================================================================
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--- lib/Target/AArch64/AArch64AsmPrinter.cpp
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+++ lib/Target/AArch64/AArch64AsmPrinter.cpp
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@@ -12,6 +12,8 @@
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//
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//===----------------------------------------------------------------------===//
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+#include "MCTargetDesc/AArch64AddressingModes.h"
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+#include "MCTargetDesc/AArch64MCExpr.h"
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#include "AArch64.h"
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#include "AArch64MCInstLower.h"
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#include "AArch64MachineFunctionInfo.h"
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@@ -494,12 +496,47 @@ void AArch64AsmPrinter::EmitInstruction(const Mach
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EmitToStreamer(OutStreamer, TmpInst);
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return;
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}
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- case AArch64::TLSDESC_BLR: {
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- MCOperand Callee, Sym;
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- MCInstLowering.lowerOperand(MI->getOperand(0), Callee);
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- MCInstLowering.lowerOperand(MI->getOperand(1), Sym);
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+ case AArch64::TLSDESC_CALLSEQ: {
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+ /// lower this to:
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+ /// adrp x0, :tlsdesc:var
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+ /// ldr x1, [x0, #:tlsdesc_lo12:var]
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+ /// add x0, x0, #:tlsdesc_lo12:var
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+ /// .tlsdesccall var
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+ /// blr x1
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+ /// (TPIDR_EL0 offset now in x0)
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+ const MachineOperand &MO_Sym = MI->getOperand(0);
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+ MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
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+ MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
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+ MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
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+ AArch64II::MO_NC);
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+ MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
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+ MCInstLowering.lowerOperand(MO_Sym, Sym);
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+ MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
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+ MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
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- // First emit a relocation-annotation. This expands to no code, but requests
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+ MCInst Adrp;
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+ Adrp.setOpcode(AArch64::ADRP);
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+ Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
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+ Adrp.addOperand(SymTLSDesc);
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+ EmitToStreamer(OutStreamer, Adrp);
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+
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+ MCInst Ldr;
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+ Ldr.setOpcode(AArch64::LDRXui);
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+ Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
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+ Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
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+ Ldr.addOperand(SymTLSDescLo12);
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+ Ldr.addOperand(MCOperand::CreateImm(0));
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+ EmitToStreamer(OutStreamer, Ldr);
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+
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+ MCInst Add;
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+ Add.setOpcode(AArch64::ADDXri);
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+ Add.addOperand(MCOperand::CreateReg(AArch64::X0));
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+ Add.addOperand(MCOperand::CreateReg(AArch64::X0));
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+ Add.addOperand(SymTLSDescLo12);
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+ Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
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+ EmitToStreamer(OutStreamer, Add);
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+
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+ // Emit a relocation-annotation. This expands to no code, but requests
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// the following instruction gets an R_AARCH64_TLSDESC_CALL.
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MCInst TLSDescCall;
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TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
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@@ -506,12 +543,10 @@ void AArch64AsmPrinter::EmitInstruction(const Mach
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TLSDescCall.addOperand(Sym);
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EmitToStreamer(OutStreamer, TLSDescCall);
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- // Other than that it's just a normal indirect call to the function loaded
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- // from the descriptor.
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- MCInst BLR;
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- BLR.setOpcode(AArch64::BLR);
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- BLR.addOperand(Callee);
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- EmitToStreamer(OutStreamer, BLR);
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+ MCInst Blr;
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+ Blr.setOpcode(AArch64::BLR);
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+ Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
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+ EmitToStreamer(OutStreamer, Blr);
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return;
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}
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Index: lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
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===================================================================
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--- lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
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+++ lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
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@@ -62,10 +62,10 @@ struct LDTLSCleanup : public MachineFunctionPass {
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for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
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++I) {
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switch (I->getOpcode()) {
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- case AArch64::TLSDESC_BLR:
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+ case AArch64::TLSDESC_CALLSEQ:
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// Make sure it's a local dynamic access.
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- if (!I->getOperand(1).isSymbol() ||
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- strcmp(I->getOperand(1).getSymbolName(), "_TLS_MODULE_BASE_"))
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+ if (!I->getOperand(0).isSymbol() ||
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+ strcmp(I->getOperand(0).getSymbolName(), "_TLS_MODULE_BASE_"))
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break;
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if (TLSBaseAddrReg)
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Index: lib/Target/AArch64/AArch64ISelLowering.cpp
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===================================================================
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--- lib/Target/AArch64/AArch64ISelLowering.cpp
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+++ lib/Target/AArch64/AArch64ISelLowering.cpp
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@@ -64,10 +64,18 @@ EnableAArch64ExtrGeneration("aarch64-extr-generati
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static cl::opt<bool>
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EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
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- cl::desc("Allow AArch64 SLI/SRI formation"),
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- cl::init(false));
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+ cl::desc("Allow AArch64 SLI/SRI formation"),
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+ cl::init(false));
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+// FIXME: The necessary dtprel relocations don't seem to be supported
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+// well in the GNU bfd and gold linkers at the moment. Therefore, by
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+// default, for now, fall back to GeneralDynamic code generation.
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+cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
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+ "aarch64-elf-ldtls-generation", cl::Hidden,
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+ cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
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+ cl::init(false));
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+
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AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
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: TargetLowering(TM) {
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Subtarget = &TM.getSubtarget<AArch64Subtarget>();
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@@ -760,7 +768,7 @@ const char *AArch64TargetLowering::getTargetNodeNa
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case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
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case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
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case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
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- case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
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+ case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
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case AArch64ISD::ADC: return "AArch64ISD::ADC";
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case AArch64ISD::SBC: return "AArch64ISD::SBC";
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case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
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@@ -3049,61 +3057,34 @@ AArch64TargetLowering::LowerDarwinGlobalTLSAddress
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/// When accessing thread-local variables under either the general-dynamic or
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/// local-dynamic system, we make a "TLS-descriptor" call. The variable will
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/// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
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-/// is a function pointer to carry out the resolution. This function takes the
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-/// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
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-/// other registers (except LR, NZCV) are preserved.
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+/// is a function pointer to carry out the resolution.
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///
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-/// Thus, the ideal call sequence on AArch64 is:
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+/// The sequence is:
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+/// adrp x0, :tlsdesc:var
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+/// ldr x1, [x0, #:tlsdesc_lo12:var]
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+/// add x0, x0, #:tlsdesc_lo12:var
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+/// .tlsdesccall var
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+/// blr x1
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+/// (TPIDR_EL0 offset now in x0)
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///
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-/// adrp x0, :tlsdesc:thread_var
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-/// ldr x8, [x0, :tlsdesc_lo12:thread_var]
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-/// add x0, x0, :tlsdesc_lo12:thread_var
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-/// .tlsdesccall thread_var
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-/// blr x8
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-/// (TPIDR_EL0 offset now in x0).
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-///
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-/// The ".tlsdesccall" directive instructs the assembler to insert a particular
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-/// relocation to help the linker relax this sequence if it turns out to be too
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-/// conservative.
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-///
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-/// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
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-/// is harmless.
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-SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
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- SDValue DescAddr, SDLoc DL,
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- SelectionDAG &DAG) const {
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+/// The above sequence must be produced unscheduled, to enable the linker to
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+/// optimize/relax this sequence.
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+/// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
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+/// above sequence, and expanded really late in the compilation flow, to ensure
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+/// the sequence is produced as per above.
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+SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
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+ SelectionDAG &DAG) const {
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EVT PtrVT = getPointerTy();
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- // The function we need to call is simply the first entry in the GOT for this
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- // descriptor, load it in preparation.
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- SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
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+ SDValue Chain = DAG.getEntryNode();
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+ SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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- // TLS calls preserve all registers except those that absolutely must be
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- // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
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- // silly).
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- const TargetRegisterInfo *TRI =
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- getTargetMachine().getSubtargetImpl()->getRegisterInfo();
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- const AArch64RegisterInfo *ARI =
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- static_cast<const AArch64RegisterInfo *>(TRI);
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- const uint32_t *Mask = ARI->getTLSCallPreservedMask();
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-
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- // The function takes only one argument: the address of the descriptor itself
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- // in X0.
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- SDValue Glue, Chain;
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- Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
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- Glue = Chain.getValue(1);
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-
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- // We're now ready to populate the argument list, as with a normal call:
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- SmallVector<SDValue, 6> Ops;
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+ SmallVector<SDValue, 2> Ops;
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Ops.push_back(Chain);
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- Ops.push_back(Func);
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Ops.push_back(SymAddr);
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- Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
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- Ops.push_back(DAG.getRegisterMask(Mask));
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- Ops.push_back(Glue);
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- SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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- Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
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- Glue = Chain.getValue(1);
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+ Chain = DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, Ops);
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+ SDValue Glue = Chain.getValue(1);
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return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
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}
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@@ -3114,9 +3095,18 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SD
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assert(Subtarget->isTargetELF() && "This function expects an ELF target");
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assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
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"ELF TLS only supported in small memory model");
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+ // Different choices can be made for the maximum size of the TLS area for a
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+ // module. For the small address model, the default TLS size is 16MiB and the
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+ // maximum TLS size is 4GiB.
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+ // FIXME: add -mtls-size command line option and make it control the 16MiB
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+ // vs. 4GiB code sequence generation.
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const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
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TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
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+ if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
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+ if (Model == TLSModel::LocalDynamic)
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+ Model = TLSModel::GeneralDynamic;
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+ }
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SDValue TPOff;
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EVT PtrVT = getPointerTy();
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@@ -3127,17 +3117,20 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SD
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if (Model == TLSModel::LocalExec) {
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SDValue HiVar = DAG.getTargetGlobalAddress(
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- GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
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+ GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
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SDValue LoVar = DAG.getTargetGlobalAddress(
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GV, DL, PtrVT, 0,
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- AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
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+ AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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- TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
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- DAG.getTargetConstant(16, MVT::i32)),
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- 0);
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- TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
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- DAG.getTargetConstant(0, MVT::i32)),
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- 0);
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+ SDValue TPWithOff_lo =
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+ SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
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+ HiVar, DAG.getTargetConstant(0, MVT::i32)),
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+ 0);
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+ SDValue TPWithOff =
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+ SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
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+ LoVar, DAG.getTargetConstant(0, MVT::i32)),
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+ 0);
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+ return TPWithOff;
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} else if (Model == TLSModel::InitialExec) {
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TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
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TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
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@@ -3152,19 +3145,6 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SD
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DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
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MFI->incNumLocalDynamicTLSAccesses();
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- // Accesses used in this sequence go via the TLS descriptor which lives in
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- // the GOT. Prepare an address we can use to handle this.
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- SDValue HiDesc = DAG.getTargetExternalSymbol(
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- "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
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- SDValue LoDesc = DAG.getTargetExternalSymbol(
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- "_TLS_MODULE_BASE_", PtrVT,
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- AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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-
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- // First argument to the descriptor call is the address of the descriptor
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- // itself.
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- SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
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- DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
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-
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// The call needs a relocation too for linker relaxation. It doesn't make
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// sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
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// the address.
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@@ -3173,40 +3153,23 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SD
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// Now we can calculate the offset from TPIDR_EL0 to this module's
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// thread-local area.
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- TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
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+ TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
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// Now use :dtprel_whatever: operations to calculate this variable's offset
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// in its thread-storage area.
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SDValue HiVar = DAG.getTargetGlobalAddress(
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- GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
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+ GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
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SDValue LoVar = DAG.getTargetGlobalAddress(
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GV, DL, MVT::i64, 0,
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- AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
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+ AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
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- SDValue DTPOff =
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- SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
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- DAG.getTargetConstant(16, MVT::i32)),
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- 0);
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- DTPOff =
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- SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
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- DAG.getTargetConstant(0, MVT::i32)),
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- 0);
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-
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- TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
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+ TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
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+ DAG.getTargetConstant(0, MVT::i32)),
|
||||
+ 0);
|
||||
+ TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
|
||||
+ DAG.getTargetConstant(0, MVT::i32)),
|
||||
+ 0);
|
||||
} else if (Model == TLSModel::GeneralDynamic) {
|
||||
- // Accesses used in this sequence go via the TLS descriptor which lives in
|
||||
- // the GOT. Prepare an address we can use to handle this.
|
||||
- SDValue HiDesc = DAG.getTargetGlobalAddress(
|
||||
- GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
|
||||
- SDValue LoDesc = DAG.getTargetGlobalAddress(
|
||||
- GV, DL, PtrVT, 0,
|
||||
- AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
|
||||
-
|
||||
- // First argument to the descriptor call is the address of the descriptor
|
||||
- // itself.
|
||||
- SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
|
||||
- DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
|
||||
-
|
||||
// The call needs a relocation too for linker relaxation. It doesn't make
|
||||
// sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
|
||||
// the address.
|
||||
@@ -3214,7 +3177,7 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SD
|
||||
DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
|
||||
|
||||
// Finally we can make a call to calculate the offset from tpidr_el0.
|
||||
- TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
|
||||
+ TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
|
||||
} else
|
||||
llvm_unreachable("Unsupported ELF TLS access model");
|
||||
|
||||
Index: lib/Target/AArch64/AArch64ISelLowering.h
|
||||
===================================================================
|
||||
--- lib/Target/AArch64/AArch64ISelLowering.h
|
||||
+++ lib/Target/AArch64/AArch64ISelLowering.h
|
||||
@@ -29,9 +29,9 @@ enum {
|
||||
WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
|
||||
CALL, // Function call.
|
||||
|
||||
- // Almost the same as a normal call node, except that a TLSDesc relocation is
|
||||
- // needed so the linker can relax it correctly if possible.
|
||||
- TLSDESC_CALL,
|
||||
+ // Produces the full sequence of instructions for getting the thread pointer
|
||||
+ // offset of a variable into X0, using the TLSDesc model.
|
||||
+ TLSDESC_CALLSEQ,
|
||||
ADRP, // Page address of a TargetGlobalAddress operand.
|
||||
ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
|
||||
LOADgot, // Load from automatically generated descriptor (e.g. Global
|
||||
@@ -399,8 +399,8 @@ class AArch64TargetLowering : public TargetLowerin
|
||||
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
||||
- SDValue LowerELFTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
|
||||
- SelectionDAG &DAG) const;
|
||||
+ SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
|
||||
+ SelectionDAG &DAG) const;
|
||||
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
|
||||
Index: lib/Target/AArch64/AArch64InstrInfo.td
|
||||
===================================================================
|
||||
--- lib/Target/AArch64/AArch64InstrInfo.td
|
||||
+++ lib/Target/AArch64/AArch64InstrInfo.td
|
||||
@@ -96,6 +96,19 @@ def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCis
|
||||
|
||||
def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
|
||||
SDTCisPtrTy<1>]>;
|
||||
+
|
||||
+// Generates the general dynamic sequences, i.e.
|
||||
+// adrp x0, :tlsdesc:var
|
||||
+// ldr x1, [x0, #:tlsdesc_lo12:var]
|
||||
+// add x0, x0, #:tlsdesc_lo12:var
|
||||
+// .tlsdesccall var
|
||||
+// blr x1
|
||||
+
|
||||
+// (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
|
||||
+// number of operands (the variable)
|
||||
+def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
|
||||
+ [SDTCisPtrTy<0>]>;
|
||||
+
|
||||
def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
|
||||
[SDTCisVT<0, i64>, SDTCisVT<1, i32>,
|
||||
SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
|
||||
@@ -229,11 +242,12 @@ def AArch64Prefetch : SDNode<"AArch64ISD::P
|
||||
def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
|
||||
def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
|
||||
|
||||
-def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
|
||||
- SDT_AArch64TLSDescCall,
|
||||
- [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
|
||||
- SDNPVariadic]>;
|
||||
+def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
|
||||
+ SDT_AArch64TLSDescCallSeq,
|
||||
+ [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
|
||||
+ SDNPVariadic]>;
|
||||
|
||||
+
|
||||
def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
|
||||
SDT_AArch64WrapperLarge>;
|
||||
|
||||
@@ -1049,15 +1063,16 @@ def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym)
|
||||
let AsmString = ".tlsdesccall $sym";
|
||||
}
|
||||
|
||||
-// Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
|
||||
-// gets expanded to two MCInsts during lowering.
|
||||
-let isCall = 1, Defs = [LR] in
|
||||
-def TLSDESC_BLR
|
||||
- : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
|
||||
- [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
|
||||
+// FIXME: maybe the scratch register used shouldn't be fixed to X1?
|
||||
+// FIXME: can "hasSideEffects be dropped?
|
||||
+let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
|
||||
+ isCodeGenOnly = 1 in
|
||||
+def TLSDESC_CALLSEQ
|
||||
+ : Pseudo<(outs), (ins i64imm:$sym),
|
||||
+ [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
|
||||
+def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
|
||||
+ (TLSDESC_CALLSEQ texternalsym:$sym)>;
|
||||
|
||||
-def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
|
||||
- (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditional branch (immediate) instruction.
|
||||
//===----------------------------------------------------------------------===//
|
||||
Index: lib/Target/AArch64/AArch64MCInstLower.cpp
|
||||
===================================================================
|
||||
--- lib/Target/AArch64/AArch64MCInstLower.cpp
|
||||
+++ lib/Target/AArch64/AArch64MCInstLower.cpp
|
||||
@@ -22,9 +22,12 @@
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/Support/CodeGen.h"
|
||||
+#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
using namespace llvm;
|
||||
|
||||
+extern cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration;
|
||||
+
|
||||
AArch64MCInstLower::AArch64MCInstLower(MCContext &ctx, AsmPrinter &printer)
|
||||
: Ctx(ctx), Printer(printer), TargetTriple(printer.getTargetTriple()) {}
|
||||
|
||||
@@ -84,10 +87,16 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandEL
|
||||
if (MO.isGlobal()) {
|
||||
const GlobalValue *GV = MO.getGlobal();
|
||||
Model = Printer.TM.getTLSModel(GV);
|
||||
+ if (!EnableAArch64ELFLocalDynamicTLSGeneration &&
|
||||
+ Model == TLSModel::LocalDynamic)
|
||||
+ Model = TLSModel::GeneralDynamic;
|
||||
+
|
||||
} else {
|
||||
assert(MO.isSymbol() &&
|
||||
StringRef(MO.getSymbolName()) == "_TLS_MODULE_BASE_" &&
|
||||
"unexpected external TLS symbol");
|
||||
+ // The general dynamic access sequence is used to get the
|
||||
+ // address of _TLS_MODULE_BASE_.
|
||||
Model = TLSModel::GeneralDynamic;
|
||||
}
|
||||
switch (Model) {
|
||||
@@ -123,6 +132,8 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandEL
|
||||
RefFlags |= AArch64MCExpr::VK_G1;
|
||||
else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_G0)
|
||||
RefFlags |= AArch64MCExpr::VK_G0;
|
||||
+ else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_HI12)
|
||||
+ RefFlags |= AArch64MCExpr::VK_HI12;
|
||||
|
||||
if (MO.getTargetFlags() & AArch64II::MO_NC)
|
||||
RefFlags |= AArch64MCExpr::VK_NC;
|
||||
Index: lib/Target/AArch64/Utils/AArch64BaseInfo.h
|
||||
===================================================================
|
||||
--- lib/Target/AArch64/Utils/AArch64BaseInfo.h
|
||||
+++ lib/Target/AArch64/Utils/AArch64BaseInfo.h
|
||||
@@ -1229,7 +1229,7 @@ namespace AArch64II {
|
||||
|
||||
MO_NO_FLAG,
|
||||
|
||||
- MO_FRAGMENT = 0x7,
|
||||
+ MO_FRAGMENT = 0xf,
|
||||
|
||||
/// MO_PAGE - A symbol operand with this flag represents the pc-relative
|
||||
/// offset of the 4K page containing the symbol. This is used with the
|
||||
@@ -1257,26 +1257,31 @@ namespace AArch64II {
|
||||
/// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
|
||||
MO_G0 = 6,
|
||||
|
||||
+ /// MO_HI12 - This flag indicates that a symbol operand represents the bits
|
||||
+ /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
|
||||
+ /// by-12-bits instruction.
|
||||
+ MO_HI12 = 7,
|
||||
+
|
||||
/// MO_GOT - This flag indicates that a symbol operand represents the
|
||||
/// address of the GOT entry for the symbol, rather than the address of
|
||||
/// the symbol itself.
|
||||
- MO_GOT = 8,
|
||||
+ MO_GOT = 0x10,
|
||||
|
||||
/// MO_NC - Indicates whether the linker is expected to check the symbol
|
||||
/// reference for overflow. For example in an ADRP/ADD pair of relocations
|
||||
/// the ADRP usually does check, but not the ADD.
|
||||
- MO_NC = 0x10,
|
||||
+ MO_NC = 0x20,
|
||||
|
||||
/// MO_TLS - Indicates that the operand being accessed is some kind of
|
||||
/// thread-local symbol. On Darwin, only one type of thread-local access
|
||||
/// exists (pre linker-relaxation), but on ELF the TLSModel used for the
|
||||
/// referee will affect interpretation.
|
||||
- MO_TLS = 0x20,
|
||||
+ MO_TLS = 0x40,
|
||||
|
||||
/// MO_CONSTPOOL - This flag indicates that a symbol operand represents
|
||||
/// the address of a constant pool entry for the symbol, rather than the
|
||||
/// address of the symbol itself.
|
||||
- MO_CONSTPOOL = 0x40
|
||||
+ MO_CONSTPOOL = 0x80
|
||||
};
|
||||
} // end namespace AArch64II
|
||||
|
||||
Index: test/CodeGen/AArch64/arm64-tls-dynamics.ll
|
||||
===================================================================
|
||||
--- test/CodeGen/AArch64/arm64-tls-dynamics.ll
|
||||
+++ test/CodeGen/AArch64/arm64-tls-dynamics.ll
|
||||
@@ -1,5 +1,7 @@
|
||||
-; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s
|
||||
-; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
|
||||
+; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -verify-machineinstrs < %s | FileCheck %s
|
||||
+; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
|
||||
+; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOLD %s
|
||||
+; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-NOLD-RELOC %s
|
||||
|
||||
@general_dynamic_var = external thread_local global i32
|
||||
|
||||
@@ -9,22 +11,34 @@ define i32 @test_generaldynamic() {
|
||||
%val = load i32* @general_dynamic_var
|
||||
ret i32 %val
|
||||
|
||||
- ; FIXME: the adrp instructions are redundant (if harmless).
|
||||
-; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
-; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
|
||||
-; CHECK: .tlsdesccall general_dynamic_var
|
||||
+; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
|
||||
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
|
||||
+; CHECK-NEXT: .tlsdesccall general_dynamic_var
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
+; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
|
||||
+; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: .tlsdesccall general_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: blr [[CALLEE]]
|
||||
+
|
||||
+
|
||||
; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
|
||||
; CHECK: ldr w0, [x[[TP]], x0]
|
||||
+; CHECK-NOLD: mrs x[[TP:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK-NOLD: ldr w0, [x[[TP]], x0]
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+
|
||||
}
|
||||
|
||||
define i32* @test_generaldynamic_addr() {
|
||||
@@ -32,12 +46,10 @@ define i32* @test_generaldynamic_addr() {
|
||||
|
||||
ret i32* @general_dynamic_var
|
||||
|
||||
- ; FIXME: the adrp instructions are redundant (if harmless).
|
||||
-; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
-; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
|
||||
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
|
||||
-; CHECK: .tlsdesccall general_dynamic_var
|
||||
+; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
|
||||
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
|
||||
+; CHECK-NEXT: .tlsdesccall general_dynamic_var
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
|
||||
@@ -44,9 +56,15 @@ define i32* @test_generaldynamic_addr() {
|
||||
; CHECK: add x0, [[TP]], x0
|
||||
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+
|
||||
}
|
||||
|
||||
@local_dynamic_var = external thread_local(localdynamic) global i32
|
||||
@@ -58,54 +76,71 @@ define i32 @test_localdynamic() {
|
||||
ret i32 %val
|
||||
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
+; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
+; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
+; CHECK-NEXT: add x[[TPOFF:[0-9]+]], x0, :dtprel_hi12:local_dynamic_var
|
||||
+; CHECK-NEXT: add x[[TPOFF]], x[[TPOFF]], :dtprel_lo12_nc:local_dynamic_var
|
||||
+; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK: ldr w0, [x[[TPIDR]], x[[TPOFF]]]
|
||||
|
||||
-; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
|
||||
-; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var
|
||||
+; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var]
|
||||
+; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: blr [[CALLEE]]
|
||||
+; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK-NOLD: ldr w0, [x[[TPIDR]], x0]
|
||||
|
||||
-; CHECK: add x[[TPREL:[0-9]+]], x0, [[DTP_OFFSET]]
|
||||
|
||||
-; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
|
||||
-
|
||||
-; CHECK: ldr w0, [x[[TPIDR]], x[[TPREL]]]
|
||||
-
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
|
||||
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+
|
||||
}
|
||||
|
||||
define i32* @test_localdynamic_addr() {
|
||||
; CHECK-LABEL: test_localdynamic_addr:
|
||||
|
||||
- ret i32* @local_dynamic_var
|
||||
-
|
||||
; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
+; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
+; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
+; CHECK-NEXT: add x[[TPOFF:[0-9]+]], x0, :dtprel_hi12:local_dynamic_var
|
||||
+; CHECK-NEXT: add x[[TPOFF]], x[[TPOFF]], :dtprel_lo12_nc:local_dynamic_var
|
||||
+; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK: add x0, x[[TPIDR]], x[[TPOFF]]
|
||||
|
||||
-; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
|
||||
-; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var
|
||||
+; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var]
|
||||
+; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var
|
||||
+; CHECK-NOLD-NEXT: blr [[CALLEE]]
|
||||
+; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK-NOLD: add x0, x[[TPIDR]], x0
|
||||
+ ret i32* @local_dynamic_var
|
||||
|
||||
-; CHECK: add [[TPREL:x[0-9]+]], x0, [[DTP_OFFSET]]
|
||||
-
|
||||
-; CHECK: mrs [[TPIDR:x[0-9]+]], TPIDR_EL0
|
||||
-
|
||||
-; CHECK: add x0, [[TPIDR]], [[TPREL]]
|
||||
-
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
|
||||
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
|
||||
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
|
||||
}
|
||||
|
||||
; The entire point of the local-dynamic access model is to have a single call to
|
||||
@@ -122,11 +157,10 @@ define i32 @test_localdynamic_deduplicate() {
|
||||
%sum = add i32 %val, %val2
|
||||
ret i32 %sum
|
||||
|
||||
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
|
||||
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
|
||||
+; CHECK: adrp x[[DTPREL_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
|
||||
+; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[DTPREL_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
|
||||
+; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE
|
||||
+; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_
|
||||
; CHECK-NEXT: blr [[CALLEE]]
|
||||
|
||||
; CHECK-NOT: _TLS_MODULE_BASE_
|
||||
Index: test/CodeGen/AArch64/arm64-tls-execs.ll
|
||||
===================================================================
|
||||
--- test/CodeGen/AArch64/arm64-tls-execs.ll
|
||||
+++ test/CodeGen/AArch64/arm64-tls-execs.ll
|
||||
@@ -38,14 +38,13 @@ define i32 @test_local_exec() {
|
||||
; CHECK-LABEL: test_local_exec:
|
||||
%val = load i32* @local_exec_var
|
||||
|
||||
-; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var // encoding: [0bAAA{{[01]+}},A,0b101AAAAA,0x92]
|
||||
-; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var
|
||||
-; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
|
||||
-; CHECK: ldr w0, [x[[TP]], [[TP_OFFSET]]]
|
||||
+; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
|
||||
+; CHECK: add x[[R3:[0-9]+]], x[[R2]], :tprel_lo12_nc:local_exec_var
|
||||
+; CHECK: ldr w0, [x[[R3]]]
|
||||
|
||||
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1
|
||||
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
|
||||
-
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
|
||||
ret i32 %val
|
||||
}
|
||||
|
||||
@@ -53,11 +52,11 @@ define i32* @test_local_exec_addr() {
|
||||
; CHECK-LABEL: test_local_exec_addr:
|
||||
ret i32* @local_exec_var
|
||||
|
||||
-; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
||||
-; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var
|
||||
-; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
|
||||
-; CHECK: add x0, [[TP]], [[TP_OFFSET]]
|
||||
+; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0
|
||||
+; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var
|
||||
+; CHECK: add x0, x[[R2]], :tprel_lo12_nc:local_exec_var
|
||||
+; CHECK: ret
|
||||
|
||||
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1
|
||||
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12
|
||||
+; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user