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[PowerPC] Fix booke64 qemu infinite loop in L2 cache enable

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Since qemu does not implement the L2 cache, we get stuck forever waiting
for a bit to be set when trying to invalidate it.

To prevent that, we should bail out if the L2 cache is missing.
One easy way to check this is L2CFG0 == 0 (since L2CSIZE always has at
least one bit set in a valid implementation)

(tested on qemu, rb800, and x5000)

Reviewed by:	jhibbits
Sponsored by:	Tag1 Consulting, Inc.
Differential Revision:	https://reviews.freebsd.org/D25225
This commit is contained in:
Brandon Bergren 2020-06-19 18:40:39 +00:00
parent 37f530582d
commit 8415f755f1
2 changed files with 12 additions and 1 deletions
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12
sys/powerpc/booke/machdep_e500.c
View File

@ -91,7 +91,17 @@ booke_enable_l2_cache(void)
if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) ||
(((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) {
csr = mfspr(SPR_L2CSR0);
if ((csr & L2CSR0_L2E) == 0) {
/*
* Don't actually attempt to manipulate the L2 cache if
* L2CFG0 is zero.
*
* Any chip with a working L2 cache will have a nonzero
* L2CFG0, as it will have a nonzero L2CSIZE field.
*
* This fixes waiting forever for cache enable in qemu,
* which does not implement the L2 cache.
*/
if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) {
l2cache_inval();
l2cache_enable();
}

1
sys/powerpc/include/spr.h
View File

@ -887,6 +887,7 @@
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */
#define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */
#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */