From 8454b1bf68a6e9d67f7a910af8a1590b0bac55c6 Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sun, 26 Aug 2012 04:39:20 +0000 Subject: [PATCH] Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registers are written out. This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly initialised. Tested: * AP91 (AR7240+AR9285) - the existing board support didn't break; * AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI. --- sys/mips/atheros/ar724x_pci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/mips/atheros/ar724x_pci.c b/sys/mips/atheros/ar724x_pci.c index 07c2c67b71d4..e73e9fc97be7 100644 --- a/sys/mips/atheros/ar724x_pci.c +++ b/sys/mips/atheros/ar724x_pci.c @@ -270,6 +270,10 @@ ar724x_pci_fixup(device_t dev, long flash_addr, int len) /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */ bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4); + /* Write temporary BAR0 to map the NIC into a fixed location */ + ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), + AR71XX_PCI_MEM_BASE, 4); + val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2); val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);