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bhndb_pci(4): fix incorrect BHND_PCI_SRSH_PI workaround

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On a SPROM-less device, the PCI(e) bridge core will be initialized with its
power-on-reset defaults; this can leave the SPROM-derived BHND_PCI_SRSH_PI
value pointing to the wrong backplane address. This value is used by the
PCI core when performing address translation between the static register
windows in BAR0 that map the PCI core's register block, and backplane
address space.

Previously, bhndb_pci(4) incorrectly used the potentially invalid static
BAR0 PCI register windows when attempting to correct the BHND_PCI_SRSH_PI
value in the PCI core's SPROM shadow.

Instead, we now read/update BHND_PCI_SRSH_PI by fetching the PCI core's
backplane address from the core enumeration table, and then using a dynamic
register window to explicitly map the PCI core's register block into BAR0.

Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Landon J. Fuller 2018-01-17 03:34:26 +00:00
parent f24882eca5
commit 84d6a5d4a7
3 changed files with 583 additions and 351 deletions
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916
sys/dev/bhnd/bhndb/bhndb_pci.c
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File diff suppressed because it is too large Load Diff

6
sys/dev/bhnd/bhndb/bhndb_pcivar.h
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@ -97,16 +97,14 @@ struct bhndb_pci_quirk {
/** bhndb_pci core table entry */
struct bhndb_pci_core {
struct bhnd_core_match match; /**< core match descriptor */
bus_size_t srsh_offset; /**< offset to SRSH_PI register, if any */
struct bhndb_pci_quirk *quirks; /**< quirk table */
};
#define BHNDB_PCI_CORE(_device, _srsh, _quirks) { \
#define BHNDB_PCI_CORE(_device, _quirks) { \
{ BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_ ## _device) }, \
_srsh, \
_quirks \
}
#define BHNDB_PCI_CORE_END { { BHND_MATCH_ANY }, 0, NULL }
#define BHNDB_PCI_CORE_END { { BHND_MATCH_ANY }, NULL }
#define BHNDB_PCI_IS_CORE_END(_c) BHND_MATCH_IS_ANY(&(_c)->match)
struct bhndb_pci_softc {

12
sys/dev/bhnd/cores/pci/bhnd_pcireg.h
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@ -129,12 +129,12 @@
#define BHND_PCI_SBTOPCI_RC_READLINE 0x10 /* memory read line */
#define BHND_PCI_SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
/* PCI core index in SROM shadow area */
/* PCI base address bits in SPROM shadow area */
#define BHND_PCI_SRSH_PI_OFFSET 0 /* first word */
#define BHND_PCI_SRSH_PI_MASK 0xf000 /* bit 15:12 */
#define BHND_PCI_SRSH_PI_SHIFT 12 /* bit 15:12 */
#define BHND_PCI_SRSH_PI_ADDR_MASK 0x0000F000
#define BHND_PCI_SRSH_PI_ADDR_SHIFT 12
/*
* PCIe-Gen1 Core Registers
@ -397,9 +397,11 @@
/* SPROM offsets */
#define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI core index in SROM shadow area */
#define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK
#define BHND_PCIE_SRSH_PI_OFFSET BHND_PCI_SRSH_PI_OFFSET /**< PCI base address bits in SPROM shadow area */
#define BHND_PCIE_SRSH_PI_MASK BHND_PCI_SRSH_PI_MASK /**< bits 15:12 of the PCI core address */
#define BHND_PCIE_SRSH_PI_SHIFT BHND_PCI_SRSH_PI_SHIFT
#define BHND_PCIE_SRSH_PI_ADDR_MASK BHND_PCI_SRSH_PI_ADDR_MASK
#define BHND_PCIE_SRSH_PI_ADDR_SHIFT BHND_PCI_SRSH_PI_ADDR_SHIFT
#define BHND_PCIE_SRSH_ASPM_OFFSET 8 /* word 4 */
#define BHND_PCIE_SRSH_ASPM_ENB 0x18 /* bit 3, 4 */