Added support for the Intel 82555 PHY chip which is being used on newer
Pro/100B cards. Full duplex should work now, although it hasn't been tested.
This commit is contained in:
David Greenman
parent
c2043f40bb
commit
854d14213e
@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.33 1997/03/25 14:54:38 davidg Exp $
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* $Id: if_fxp.c,v 1.34 1997/04/23 01:44:30 davidg Exp $
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*/
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/*
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@ -963,15 +963,18 @@ fxp_init(xsc)
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csr->scb_command = FXP_SCB_COMMAND_RU_START;
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/*
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* Toggle a few bits in the DP83840 PHY.
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* Toggle a few bits in the PHY.
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*/
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if (sc->phy_primary_device == FXP_PHY_DP83840 ||
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sc->phy_primary_device == FXP_PHY_DP83840A) {
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switch (sc->phy_primary_device) {
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case FXP_PHY_DP83840:
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case FXP_PHY_DP83840A:
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
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fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
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FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
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FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
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FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
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/* fall through */
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case FXP_PHY_82555:
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/*
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* If link0 is set, disable auto-negotiation and then:
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* If link1 is unset = 10Mbps
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@ -983,19 +986,20 @@ fxp_init(xsc)
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int flags;
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flags = (ifp->if_flags & IFF_LINK1) ?
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FXP_DP83840_BMCR_SPEED_100M : 0;
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FXP_PHY_BMCR_SPEED_100M : 0;
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flags |= (ifp->if_flags & IFF_LINK2) ?
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FXP_DP83840_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) &
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~(FXP_DP83840_BMCR_AUTOEN | FXP_DP83840_BMCR_SPEED_100M |
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FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
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FXP_PHY_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) &
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~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
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FXP_PHY_BMCR_FULLDUPLEX)) | flags);
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} else {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) |
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FXP_DP83840_BMCR_AUTOEN));
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) |
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FXP_PHY_BMCR_AUTOEN));
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}
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} else {
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break;
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default:
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printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
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ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
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}
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.7 1997/03/17 11:08:16 davidg Exp $
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* $Id: if_fxpreg.h,v 1.8 1997/03/21 08:00:13 davidg Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -292,15 +292,16 @@ struct fxp_stats {
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_82555 7
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#define FXP_PHY_DP83840A 10
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/*
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* DP84830 PHY, BMCR Basic Mode Control Register
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* PHY BMCR Basic Mode Control Register
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*/
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#define FXP_DP83840_BMCR 0x0
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#define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
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#define FXP_DP83840_BMCR_AUTOEN 0x1000
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#define FXP_DP83840_BMCR_SPEED_100M 0x2000
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
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#define FXP_PHY_BMCR_AUTOEN 0x1000
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#define FXP_PHY_BMCR_SPEED_100M 0x2000
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/*
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* DP84830 PHY, PCS Configuration Register
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.33 1997/03/25 14:54:38 davidg Exp $
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* $Id: if_fxp.c,v 1.34 1997/04/23 01:44:30 davidg Exp $
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*/
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/*
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@ -963,15 +963,18 @@ fxp_init(xsc)
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csr->scb_command = FXP_SCB_COMMAND_RU_START;
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/*
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* Toggle a few bits in the DP83840 PHY.
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* Toggle a few bits in the PHY.
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*/
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if (sc->phy_primary_device == FXP_PHY_DP83840 ||
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sc->phy_primary_device == FXP_PHY_DP83840A) {
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switch (sc->phy_primary_device) {
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case FXP_PHY_DP83840:
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case FXP_PHY_DP83840A:
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR,
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fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_PCR) |
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FXP_DP83840_PCR_LED4_MODE | /* LED4 always indicates duplex */
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FXP_DP83840_PCR_F_CONNECT | /* force link disconnect bypass */
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FXP_DP83840_PCR_BIT10); /* XXX I have no idea */
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/* fall through */
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case FXP_PHY_82555:
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/*
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* If link0 is set, disable auto-negotiation and then:
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* If link1 is unset = 10Mbps
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@ -983,19 +986,20 @@ fxp_init(xsc)
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int flags;
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flags = (ifp->if_flags & IFF_LINK1) ?
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FXP_DP83840_BMCR_SPEED_100M : 0;
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FXP_PHY_BMCR_SPEED_100M : 0;
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flags |= (ifp->if_flags & IFF_LINK2) ?
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FXP_DP83840_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) &
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~(FXP_DP83840_BMCR_AUTOEN | FXP_DP83840_BMCR_SPEED_100M |
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FXP_DP83840_BMCR_FULLDUPLEX)) | flags);
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FXP_PHY_BMCR_FULLDUPLEX : 0;
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) &
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~(FXP_PHY_BMCR_AUTOEN | FXP_PHY_BMCR_SPEED_100M |
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FXP_PHY_BMCR_FULLDUPLEX)) | flags);
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} else {
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_DP83840_BMCR) |
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FXP_DP83840_BMCR_AUTOEN));
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fxp_mdi_write(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR,
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(fxp_mdi_read(sc->csr, sc->phy_primary_addr, FXP_PHY_BMCR) |
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FXP_PHY_BMCR_AUTOEN));
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}
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} else {
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break;
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default:
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printf("fxp%d: warning: unsupported PHY, type = %d, addr = %d\n",
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ifp->if_unit, sc->phy_primary_device, sc->phy_primary_addr);
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}
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.7 1997/03/17 11:08:16 davidg Exp $
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* $Id: if_fxpreg.h,v 1.8 1997/03/21 08:00:13 davidg Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -292,15 +292,16 @@ struct fxp_stats {
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#define FXP_PHY_DP83840 4
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#define FXP_PHY_80C240 5
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#define FXP_PHY_80C24 6
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#define FXP_PHY_82555 7
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#define FXP_PHY_DP83840A 10
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/*
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* DP84830 PHY, BMCR Basic Mode Control Register
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* PHY BMCR Basic Mode Control Register
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*/
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#define FXP_DP83840_BMCR 0x0
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#define FXP_DP83840_BMCR_FULLDUPLEX 0x0100
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#define FXP_DP83840_BMCR_AUTOEN 0x1000
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#define FXP_DP83840_BMCR_SPEED_100M 0x2000
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
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#define FXP_PHY_BMCR_AUTOEN 0x1000
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#define FXP_PHY_BMCR_SPEED_100M 0x2000
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/*
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* DP84830 PHY, PCS Configuration Register
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