Support multi-port PCIe hierarchy in Marvell boards DTS
This commit is another part of preparation for PCIe multi-port support for Marvell SoCs. Some device trees include pcie-controller node as a bus-parent of pcie nodes. This patch adds support for new bus, collects and configures device informations and finally adds PCIB devices as a childs of pcie-controller in Newbus hierarchy. Submitted by: Marcin Mazurek <mma@semihalf.com> Obtained form: Semihalf Sponsored by: Stormshield Reviewed by: https://reviews.freebsd.org/D10906
This commit is contained in:
Zbigniew Bodek
parent
73e48bc6d6
commit
8595864992
@ -16,6 +16,7 @@ arm/mv/gpio.c optional gpio
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arm/mv/mv_common.c standard
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arm/mv/mv_localbus.c standard
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arm/mv/mv_machdep.c standard
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arm/mv/mv_pci_ctrl.c optional pci | fdt
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arm/mv/mv_pci.c optional pci
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arm/mv/mv_ts.c standard
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arm/mv/timer.c optional !soc_mv_armada38x
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@ -394,6 +394,7 @@ static driver_t mv_pcib_driver = {
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devclass_t pcib_devclass;
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DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
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DRIVER_MODULE(pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
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static struct mtx pcicfg_mtx;
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@ -419,21 +420,29 @@ mv_pcib_attach(device_t self)
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{
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struct mv_pcib_softc *sc;
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phandle_t node, parnode;
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uint32_t val, unit;
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int err;
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uint32_t val, reg0;
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int err, bus, devfn, port_id;
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sc = device_get_softc(self);
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sc->sc_dev = self;
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unit = fdt_get_unit(self);
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node = ofw_bus_get_node(self);
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parnode = OF_parent(node);
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if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
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sizeof(port_id)) <= 0) {
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/* If port ID does not exist in the FDT set value to 0 */
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if (!OF_hasprop(node, "marvell,pcie-port"))
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port_id = 0;
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else
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return(ENXIO);
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}
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if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
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sc->sc_type = MV_TYPE_PCIE;
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sc->sc_win_target = MV_WIN_PCIE_TARGET(unit);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit);
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sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
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sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
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sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
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} else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
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sc->sc_type = MV_TYPE_PCI;
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sc->sc_win_target = MV_WIN_PCI_TARGET;
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@ -476,7 +485,7 @@ mv_pcib_attach(device_t self)
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/*
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* Enable PCIE device.
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*/
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mv_pcib_enable(sc, unit);
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mv_pcib_enable(sc, port_id);
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/*
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* Memory management.
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@ -485,6 +494,22 @@ mv_pcib_attach(device_t self)
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if (err)
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return (err);
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/*
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* Preliminary bus enumeration to find first linked devices and set
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* appropriate bus number from which should start the actual enumeration
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*/
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for (bus = 0; bus < PCI_BUSMAX; bus++) {
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for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
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reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
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if (reg0 == (~0U))
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continue; /* no device */
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else {
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sc->sc_busnr = bus; /* update bus number */
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break;
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}
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}
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}
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if (sc->sc_mode == MV_MODE_ROOT) {
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err = mv_pcib_init(sc, sc->sc_busnr,
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mv_pcib_maxslots(sc->sc_dev));
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333
sys/arm/mv/mv_pci_ctrl.c
Normal file
333
sys/arm/mv/mv_pci_ctrl.c
Normal file
@ -0,0 +1,333 @@
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/*-
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* Copyright (c) 2016 Stormshield
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* Copyright (c) 2016 Semihalf
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Portions of this software were developed by Semihalf
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Marvell integrated PCI/PCI-Express Bus Controller Driver.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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static int mv_pcib_ctrl_probe(device_t);
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static int mv_pcib_ctrl_attach(device_t);
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static device_t mv_pcib_ctrl_add_child(device_t, u_int, const char *, int);
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static const struct ofw_bus_devinfo * mv_pcib_ctrl_get_devinfo(device_t, device_t);
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static struct resource * mv_pcib_ctrl_alloc_resource(device_t, device_t, int,
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int *, rman_res_t, rman_res_t, rman_res_t, u_int);
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void mv_pcib_ctrl_init(device_t, phandle_t);
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static int mv_pcib_ofw_bus_attach(device_t);
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struct mv_pcib_ctrl_range {
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uint64_t bus;
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uint64_t host;
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uint64_t size;
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};
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struct mv_pcib_ctrl_softc {
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pcell_t addr_cells;
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pcell_t size_cells;
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int nranges;
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struct mv_pcib_ctrl_range *ranges;
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};
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struct mv_pcib_ctrl_devinfo {
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struct ofw_bus_devinfo di_dinfo;
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struct resource_list di_rl;
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};
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static int mv_pcib_ctrl_fill_ranges(phandle_t, struct mv_pcib_ctrl_softc *);
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/*
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* Bus interface definitions
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*/
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static device_method_t mv_pcib_ctrl_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mv_pcib_ctrl_probe),
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DEVMETHOD(device_attach, mv_pcib_ctrl_attach),
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/* Bus interface */
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DEVMETHOD(bus_add_child, mv_pcib_ctrl_add_child),
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DEVMETHOD(bus_alloc_resource, mv_pcib_ctrl_alloc_resource),
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DEVMETHOD(bus_release_resource, bus_generic_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_devinfo, mv_pcib_ctrl_get_devinfo),
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DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
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DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
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DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
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DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
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DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
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DEVMETHOD_END
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};
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static driver_t mv_pcib_ctrl_driver = {
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"pcib_ctrl",
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mv_pcib_ctrl_methods,
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sizeof(struct mv_pcib_ctrl_softc),
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};
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devclass_t pcib_ctrl_devclass;
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DRIVER_MODULE(pcib_ctrl, simplebus, mv_pcib_ctrl_driver, pcib_ctrl_devclass, 0, 0);
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MALLOC_DEFINE(M_PCIB_CTRL, "PCIe Bus Controller",
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"Marvell Integrated PCIe Bus Controller");
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static int
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mv_pcib_ctrl_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "mrvl,pcie-ctrl") &&
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!ofw_bus_is_compatible(dev, "marvell,armada-370-pcie"))
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mv_pcib_ctrl_attach(device_t dev)
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{
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int err;
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err = mv_pcib_ofw_bus_attach(dev);
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if (err != 0)
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return (err);
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return (bus_generic_attach(dev));
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}
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static int
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mv_pcib_ofw_bus_attach(device_t dev)
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{
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struct mv_pcib_ctrl_devinfo *di;
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struct mv_pcib_ctrl_softc *sc;
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device_t child;
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phandle_t parent, node;
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parent = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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if (parent > 0) {
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sc->addr_cells = 1;
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if (OF_getencprop(parent, "#address-cells", &(sc->addr_cells),
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sizeof(sc->addr_cells)) <= 0)
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return(ENXIO);
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sc->size_cells = 1;
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if (OF_getencprop(parent, "#size-cells", &(sc->size_cells),
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sizeof(sc->size_cells)) <= 0)
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return(ENXIO);
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for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
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di = malloc(sizeof(*di), M_PCIB_CTRL, M_WAITOK | M_ZERO);
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if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node)) {
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if (bootverbose) {
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device_printf(dev,
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"Could not set up devinfo for PCI\n");
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}
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free(di, M_PCIB_CTRL);
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continue;
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}
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child = device_add_child(dev, NULL, -1);
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if (child == NULL) {
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if (bootverbose) {
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device_printf(dev,
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"Could not add child: %s\n",
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di->di_dinfo.obd_name);
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}
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ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
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free(di, M_PCIB_CTRL);
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continue;
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}
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resource_list_init(&di->di_rl);
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ofw_bus_reg_to_rl(child, node, sc->addr_cells,
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sc->size_cells, &di->di_rl);
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device_set_ivars(child, di);
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}
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}
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if (mv_pcib_ctrl_fill_ranges(parent, sc) < 0) {
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device_printf(dev, "could not get ranges\n");
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return (ENXIO);
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}
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return (0);
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}
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static device_t
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mv_pcib_ctrl_add_child(device_t dev, u_int order, const char *name, int unit)
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{
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device_t cdev;
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struct mv_pcib_ctrl_devinfo *di;
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cdev = device_add_child_ordered(dev, order, name, unit);
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if (cdev == NULL)
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return (NULL);
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di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO);
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di->di_dinfo.obd_node = -1;
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resource_list_init(&di->di_rl);
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device_set_ivars(cdev, di);
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return (cdev);
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}
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static struct resource *
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mv_pcib_ctrl_alloc_resource(device_t bus, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct mv_pcib_ctrl_devinfo *di;
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struct resource_list_entry *rle;
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struct mv_pcib_ctrl_softc *sc;
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int i;
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if (RMAN_IS_DEFAULT_RANGE(start, end)) {
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if ((di = device_get_ivars(child)) == NULL)
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return (NULL);
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if (type != SYS_RES_MEMORY)
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return (NULL);
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/* Find defaults for this rid */
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rle = resource_list_find(&di->di_rl, type, *rid);
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if (rle == NULL)
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return (NULL);
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start = rle->start;
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end = rle->end;
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count = rle->count;
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}
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sc = device_get_softc(bus);
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if (type == SYS_RES_MEMORY) {
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/* Remap through ranges property */
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for (i = 0; i < sc->nranges; i++) {
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if (start >= sc->ranges[i].bus && end <
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sc->ranges[i].bus + sc->ranges[i].size) {
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start -= sc->ranges[i].bus;
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start += sc->ranges[i].host;
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end -= sc->ranges[i].bus;
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end += sc->ranges[i].host;
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break;
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}
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}
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if (i == sc->nranges && sc->nranges != 0) {
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device_printf(bus, "Could not map resource "
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"%#llx-%#llx\n", start, end);
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return (NULL);
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}
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}
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return (bus_generic_alloc_resource(bus, child, type, rid, start, end,
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count, flags));
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}
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static int
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mv_pcib_ctrl_fill_ranges(phandle_t node, struct mv_pcib_ctrl_softc *sc)
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{
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int host_address_cells;
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cell_t *base_ranges;
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ssize_t nbase_ranges;
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int err;
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int i, j, k;
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err = OF_searchencprop(OF_parent(node), "#address-cells",
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&host_address_cells, sizeof(host_address_cells));
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if (err <= 0)
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return (-1);
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nbase_ranges = OF_getproplen(node, "ranges");
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if (nbase_ranges < 0)
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return (-1);
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sc->nranges = nbase_ranges / sizeof(cell_t) /
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(sc->addr_cells + host_address_cells + sc->size_cells);
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if (sc->nranges == 0)
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return (0);
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sc->ranges = malloc(sc->nranges * sizeof(sc->ranges[0]),
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M_DEVBUF, M_WAITOK);
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base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK);
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OF_getencprop(node, "ranges", base_ranges, nbase_ranges);
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for (i = 0, j = 0; i < sc->nranges; i++) {
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sc->ranges[i].bus = 0;
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for (k = 0; k < sc->addr_cells; k++) {
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sc->ranges[i].bus <<= 32;
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sc->ranges[i].bus |= base_ranges[j++];
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}
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sc->ranges[i].host = 0;
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for (k = 0; k < host_address_cells; k++) {
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sc->ranges[i].host <<= 32;
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sc->ranges[i].host |= base_ranges[j++];
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}
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sc->ranges[i].size = 0;
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for (k = 0; k < sc->size_cells; k++) {
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sc->ranges[i].size <<= 32;
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sc->ranges[i].size |= base_ranges[j++];
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}
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}
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free(base_ranges, M_DEVBUF);
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return (sc->nranges);
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}
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static const struct ofw_bus_devinfo *
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mv_pcib_ctrl_get_devinfo(device_t bus __unused, device_t child)
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{
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struct mv_pcib_ctrl_devinfo *di;
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di = device_get_ivars(child);
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return (&di->di_dinfo);
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}
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