Be consistent about functions being static.

Properly put macro args in ().

Spotted by:	FlexeLint.
This commit is contained in:
Poul-Henning Kamp 2002-10-16 09:14:59 +00:00
parent 6dbb527e47
commit 88647b6de5
7 changed files with 31 additions and 31 deletions

@ -211,10 +211,10 @@ DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
#define SF_SETBIT(sc, reg, x) \
csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
#define SF_CLRBIT(sc, reg, x) \
csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
static u_int32_t
csr_read_4(sc, reg)

@ -201,35 +201,35 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
#define VR_SETBIT(sc, reg, x) \
CSR_WRITE_1(sc, reg, \
CSR_READ_1(sc, reg) | x)
CSR_READ_1(sc, reg) | (x))
#define VR_CLRBIT(sc, reg, x) \
CSR_WRITE_1(sc, reg, \
CSR_READ_1(sc, reg) & ~x)
CSR_READ_1(sc, reg) & ~(x))
#define VR_SETBIT16(sc, reg, x) \
CSR_WRITE_2(sc, reg, \
CSR_READ_2(sc, reg) | x)
CSR_READ_2(sc, reg) | (x))
#define VR_CLRBIT16(sc, reg, x) \
CSR_WRITE_2(sc, reg, \
CSR_READ_2(sc, reg) & ~x)
CSR_READ_2(sc, reg) & ~(x))
#define VR_SETBIT32(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
CSR_READ_4(sc, reg) | (x))
#define VR_CLRBIT32(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
CSR_WRITE_1(sc, VR_MIICMD, \
CSR_READ_1(sc, VR_MIICMD) | x)
CSR_READ_1(sc, VR_MIICMD) | (x))
#define SIO_CLR(x) \
CSR_WRITE_1(sc, VR_MIICMD, \
CSR_READ_1(sc, VR_MIICMD) & ~x)
CSR_READ_1(sc, VR_MIICMD) & ~(x))
/*
* Sync the PHYs by setting data bit and strobing the clock 32 times.
@ -1062,7 +1062,7 @@ vr_rxeof(sc)
return;
}
void
static void
vr_rxeoc(sc)
struct vr_softc *sc;
{

@ -387,11 +387,11 @@ rl_read_eeprom(sc, dest, off, cnt, swap)
*/
#define MII_SET(x) \
CSR_WRITE_1(sc, RL_MII, \
CSR_READ_1(sc, RL_MII) | x)
CSR_READ_1(sc, RL_MII) | (x))
#define MII_CLR(x) \
CSR_WRITE_1(sc, RL_MII, \
CSR_READ_1(sc, RL_MII) & ~x)
CSR_READ_1(sc, RL_MII) & ~(x))
/*
* Sync the PHYs by setting data bit and strobing the clock 32 times.

@ -211,10 +211,10 @@ DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
#define SF_SETBIT(sc, reg, x) \
csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
#define SF_CLRBIT(sc, reg, x) \
csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
static u_int32_t
csr_read_4(sc, reg)

@ -201,35 +201,35 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
#define VR_SETBIT(sc, reg, x) \
CSR_WRITE_1(sc, reg, \
CSR_READ_1(sc, reg) | x)
CSR_READ_1(sc, reg) | (x))
#define VR_CLRBIT(sc, reg, x) \
CSR_WRITE_1(sc, reg, \
CSR_READ_1(sc, reg) & ~x)
CSR_READ_1(sc, reg) & ~(x))
#define VR_SETBIT16(sc, reg, x) \
CSR_WRITE_2(sc, reg, \
CSR_READ_2(sc, reg) | x)
CSR_READ_2(sc, reg) | (x))
#define VR_CLRBIT16(sc, reg, x) \
CSR_WRITE_2(sc, reg, \
CSR_READ_2(sc, reg) & ~x)
CSR_READ_2(sc, reg) & ~(x))
#define VR_SETBIT32(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
CSR_READ_4(sc, reg) | (x))
#define VR_CLRBIT32(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
CSR_WRITE_1(sc, VR_MIICMD, \
CSR_READ_1(sc, VR_MIICMD) | x)
CSR_READ_1(sc, VR_MIICMD) | (x))
#define SIO_CLR(x) \
CSR_WRITE_1(sc, VR_MIICMD, \
CSR_READ_1(sc, VR_MIICMD) & ~x)
CSR_READ_1(sc, VR_MIICMD) & ~(x))
/*
* Sync the PHYs by setting data bit and strobing the clock 32 times.
@ -1062,7 +1062,7 @@ vr_rxeof(sc)
return;
}
void
static void
vr_rxeoc(sc)
struct vr_softc *sc;
{

@ -227,19 +227,19 @@ DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
#define WB_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | x)
CSR_READ_4(sc, reg) | (x))
#define WB_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~x)
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
CSR_WRITE_4(sc, WB_SIO, \
CSR_READ_4(sc, WB_SIO) | x)
CSR_READ_4(sc, WB_SIO) | (x))
#define SIO_CLR(x) \
CSR_WRITE_4(sc, WB_SIO, \
CSR_READ_4(sc, WB_SIO) & ~x)
CSR_READ_4(sc, WB_SIO) & ~(x))
/*
* Send a read command and address to the EEPROM, check for ACK.
@ -1212,7 +1212,7 @@ wb_rxeof(sc)
}
}
void
static void
wb_rxeoc(sc)
struct wb_softc *sc;
{

@ -350,11 +350,11 @@ xl_wait(sc)
*/
#define MII_SET(x) \
CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
#define MII_CLR(x) \
CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
/*
* Sync the PHYs by setting data bit and strobing the clock 32 times.