Be consistent about functions being static.
Properly put macro args in (). Spotted by: FlexeLint.
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6dbb527e47
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88647b6de5
@ -211,10 +211,10 @@ DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
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DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
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#define SF_SETBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
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csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
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#define SF_CLRBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
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csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
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static u_int32_t
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csr_read_4(sc, reg)
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@ -201,35 +201,35 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
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#define VR_SETBIT(sc, reg, x) \
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CSR_WRITE_1(sc, reg, \
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CSR_READ_1(sc, reg) | x)
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CSR_READ_1(sc, reg) | (x))
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#define VR_CLRBIT(sc, reg, x) \
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CSR_WRITE_1(sc, reg, \
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CSR_READ_1(sc, reg) & ~x)
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CSR_READ_1(sc, reg) & ~(x))
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#define VR_SETBIT16(sc, reg, x) \
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CSR_WRITE_2(sc, reg, \
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CSR_READ_2(sc, reg) | x)
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CSR_READ_2(sc, reg) | (x))
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#define VR_CLRBIT16(sc, reg, x) \
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CSR_WRITE_2(sc, reg, \
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CSR_READ_2(sc, reg) & ~x)
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CSR_READ_2(sc, reg) & ~(x))
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#define VR_SETBIT32(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) | x)
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CSR_READ_4(sc, reg) | (x))
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#define VR_CLRBIT32(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) & ~x)
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CSR_READ_4(sc, reg) & ~(x))
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#define SIO_SET(x) \
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CSR_WRITE_1(sc, VR_MIICMD, \
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CSR_READ_1(sc, VR_MIICMD) | x)
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CSR_READ_1(sc, VR_MIICMD) | (x))
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#define SIO_CLR(x) \
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CSR_WRITE_1(sc, VR_MIICMD, \
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CSR_READ_1(sc, VR_MIICMD) & ~x)
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CSR_READ_1(sc, VR_MIICMD) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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@ -1062,7 +1062,7 @@ vr_rxeof(sc)
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return;
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}
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void
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static void
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vr_rxeoc(sc)
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struct vr_softc *sc;
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{
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@ -387,11 +387,11 @@ rl_read_eeprom(sc, dest, off, cnt, swap)
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*/
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#define MII_SET(x) \
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CSR_WRITE_1(sc, RL_MII, \
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CSR_READ_1(sc, RL_MII) | x)
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CSR_READ_1(sc, RL_MII) | (x))
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#define MII_CLR(x) \
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CSR_WRITE_1(sc, RL_MII, \
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CSR_READ_1(sc, RL_MII) & ~x)
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CSR_READ_1(sc, RL_MII) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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@ -211,10 +211,10 @@ DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
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DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
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#define SF_SETBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
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csr_write_4(sc, reg, csr_read_4(sc, reg) | (x))
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#define SF_CLRBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
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csr_write_4(sc, reg, csr_read_4(sc, reg) & ~(x))
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static u_int32_t
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csr_read_4(sc, reg)
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@ -201,35 +201,35 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
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#define VR_SETBIT(sc, reg, x) \
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CSR_WRITE_1(sc, reg, \
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CSR_READ_1(sc, reg) | x)
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CSR_READ_1(sc, reg) | (x))
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#define VR_CLRBIT(sc, reg, x) \
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CSR_WRITE_1(sc, reg, \
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CSR_READ_1(sc, reg) & ~x)
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CSR_READ_1(sc, reg) & ~(x))
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#define VR_SETBIT16(sc, reg, x) \
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CSR_WRITE_2(sc, reg, \
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CSR_READ_2(sc, reg) | x)
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CSR_READ_2(sc, reg) | (x))
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#define VR_CLRBIT16(sc, reg, x) \
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CSR_WRITE_2(sc, reg, \
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CSR_READ_2(sc, reg) & ~x)
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CSR_READ_2(sc, reg) & ~(x))
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#define VR_SETBIT32(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) | x)
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CSR_READ_4(sc, reg) | (x))
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#define VR_CLRBIT32(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) & ~x)
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CSR_READ_4(sc, reg) & ~(x))
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#define SIO_SET(x) \
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CSR_WRITE_1(sc, VR_MIICMD, \
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CSR_READ_1(sc, VR_MIICMD) | x)
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CSR_READ_1(sc, VR_MIICMD) | (x))
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#define SIO_CLR(x) \
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CSR_WRITE_1(sc, VR_MIICMD, \
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CSR_READ_1(sc, VR_MIICMD) & ~x)
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CSR_READ_1(sc, VR_MIICMD) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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@ -1062,7 +1062,7 @@ vr_rxeof(sc)
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return;
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}
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void
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static void
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vr_rxeoc(sc)
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struct vr_softc *sc;
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{
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@ -227,19 +227,19 @@ DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
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#define WB_SETBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) | x)
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CSR_READ_4(sc, reg) | (x))
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#define WB_CLRBIT(sc, reg, x) \
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CSR_WRITE_4(sc, reg, \
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CSR_READ_4(sc, reg) & ~x)
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CSR_READ_4(sc, reg) & ~(x))
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#define SIO_SET(x) \
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CSR_WRITE_4(sc, WB_SIO, \
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CSR_READ_4(sc, WB_SIO) | x)
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CSR_READ_4(sc, WB_SIO) | (x))
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#define SIO_CLR(x) \
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CSR_WRITE_4(sc, WB_SIO, \
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CSR_READ_4(sc, WB_SIO) & ~x)
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CSR_READ_4(sc, WB_SIO) & ~(x))
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/*
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* Send a read command and address to the EEPROM, check for ACK.
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@ -1212,7 +1212,7 @@ wb_rxeof(sc)
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}
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}
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void
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static void
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wb_rxeoc(sc)
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struct wb_softc *sc;
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{
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@ -350,11 +350,11 @@ xl_wait(sc)
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*/
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#define MII_SET(x) \
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CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
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CSR_READ_2(sc, XL_W4_PHY_MGMT) | x)
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CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
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#define MII_CLR(x) \
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CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
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CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x)
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CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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