powerpc: Axe PPC4xx support.
Summary: The support was added almost a decade ago, and never completed. Just axe it. It was also inadvertently broken 5 years ago, and nobody noticed. Reviewed by: bdragon Differential Revision: https://reviews.freebsd.org/D23753
This commit is contained in:
Justin Hibbits
parent
a8f48cf82f
commit
889d304bb4
@ -4,7 +4,6 @@
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AIM opt_global.h
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BOOKE opt_global.h
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BOOKE_E500 opt_global.h
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BOOKE_PPC4XX opt_global.h
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CELL
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POWERPC
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@ -52,12 +52,6 @@ extern void l2cache_enable(void);
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extern void l2cache_inval(void);
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extern void bpred_enable(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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}
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void
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booke_enable_l1_cache(void)
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{
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@ -1,216 +0,0 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/machdep.h>
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#include <powerpc/booke/dcr.h>
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#include <powerpc/apm86xxx/apm86xxx.h>
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#include <dev/fdt/fdt_common.h>
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#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF))
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#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32))
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extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t,
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uint32_t);
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extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *,
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uint32_t *, uint32_t *);
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unsigned int tlb_static_entries;
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unsigned int tlb_current_entry = TLB_SIZE;
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unsigned int tlb_misses = 0;
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unsigned int tlb_invals = 0;
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void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);
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void tlb_map_mem(uint32_t, uint32_t, uint32_t);
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void tlb_dump(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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/* Map register space */
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tlb_map(APM86XXX_DEEP_SLEEP_VA,
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OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA),
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OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA),
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OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_PRIMARY_FABRIC_VA,
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OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA),
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OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA),
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OCP_ADDR_WORDHI(APM86XXX_AHB_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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/* Map MailBox space */
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tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA),
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x1000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x2000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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}
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void
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booke_enable_l1_cache(void)
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{
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}
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void
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booke_enable_l2_cache(void)
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{
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}
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void
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booke_disable_l2_cache(void)
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{
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uint32_t ccr1,l2cr0;
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/* Disable L2 cache op broadcast */
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ccr1 = mfspr(SPR_CCR1);
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ccr1 &= ~CCR1_L2COBE;
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mtspr(SPR_CCR1, ccr1);
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/* Set L2 array size to 0 i.e. disable L2 cache */
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mtdcr(DCR_L2DCDCRAI, DCR_L2CR0);
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l2cr0 = mfdcr(DCR_L2DCDCRDI);
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l2cr0 &= ~L2CR0_AS;
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mtdcr(DCR_L2DCDCRDI, l2cr0);
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}
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void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags,
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uint32_t perms)
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{
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tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms);
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}
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static void tlb_dump_entry(u_int entry)
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{
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uint32_t epn, rpn, erpn, tid, flags, perms;
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const char *size;
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tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms);
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switch (flags & TLB_SIZE_MASK) {
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case TLB_SIZE_1K:
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size = " 1k";
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break;
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case TLB_SIZE_4K:
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size = " 4k";
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break;
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case TLB_SIZE_16K:
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size = " 16k";
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break;
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case TLB_SIZE_256K:
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size = "256k";
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break;
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case TLB_SIZE_1M:
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size = " 1M";
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break;
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case TLB_SIZE_16M:
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size = " 16M";
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break;
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case TLB_SIZE_256M:
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size = "256M";
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break;
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case TLB_SIZE_1G:
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size = " 1G";
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break;
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default:
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size = "????";
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break;
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}
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printf("TLB[%02u]: 0x%08X => "
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"0x%01X_%08X %s %c %c %s %s %s %s %s "
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"%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n",
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entry, epn, erpn, rpn, size,
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(flags & TLB_TS) ? '1' : '0',
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(flags & TLB_VALID) ? 'V' : '.',
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(perms & TLB_WL1) ? "WL1" : "___",
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(perms & TLB_IL1I) ? "IL1I" : "____",
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(perms & TLB_IL1D) ? "IL1D" : "____",
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(perms & TLB_IL2I) ? "IL2I" : "____",
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(perms & TLB_IL2D) ? "IL2D" : "____",
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(perms & TLB_U0) ? '1' : '.',
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(perms & TLB_U1) ? '2' : '.',
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(perms & TLB_U2) ? '3' : '.',
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(perms & TLB_U3) ? '4' : '.',
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(perms & TLB_W) ? 'W' : '.',
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(perms & TLB_I) ? 'I' : '.',
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(perms & TLB_M) ? 'M' : '.',
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(perms & TLB_G) ? 'G' : '.',
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(perms & TLB_E) ? 'E' : '.',
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(perms & TLB_UX) ? 'x' : '.',
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(perms & TLB_UW) ? 'w' : '.',
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(perms & TLB_UR) ? 'r' : '.',
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(perms & TLB_SX) ? 'X' : '.',
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(perms & TLB_SW) ? 'W' : '.',
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(perms & TLB_SR) ? 'R' : '.',
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tid);
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}
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void tlb_dump(void)
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{
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int i;
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for (i = 0; i < TLB_SIZE; i++)
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tlb_dump_entry(i);
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}
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@ -36,7 +36,6 @@ options KDTRACE_HOOKS
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# You must specify at least one CPU (the one you intend to run on).
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cpu AIM
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#cpu BOOKE_E500
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#cpu BOOKE_PPC440
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options FPU_EMU
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@ -35,6 +35,5 @@ void booke_disable_l2_cache(void);
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void booke_enable_l1_cache(void);
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void booke_enable_l2_cache(void);
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void booke_enable_bpred(void);
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void booke_init_tlb(vm_paddr_t);
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#endif /* _POWERPC_MACHDEP_H_ */
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@ -190,7 +190,7 @@ extern char interrupt_vector_base[];
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extern char interrupt_vector_top[];
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#define __PROFILE_VECTOR_BASE (uintfptr_t)interrupt_vector_base
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#define __PROFILE_VECTOR_TOP (uintfptr_t)interrupt_vector_top
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#endif /* BOOKE_E500 || BOOKE_PPC4XX */
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#endif /* BOOKE_E500 */
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#endif /* !COMPILING_LINT */
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@ -241,24 +241,6 @@ typedef uint64_t pte_t;
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#define PTE_PS_SHIFT 8
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#define PTE_PS_4KB (2 << PTE_PS_SHIFT)
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#elif defined(BOOKE_PPC4XX)
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#define PTE_WL1 TLB_WL1
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#define PTE_IL2I TLB_IL2I
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#define PTE_IL2D TLB_IL2D
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#define PTE_W TLB_W
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#define PTE_I TLB_I
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#define PTE_M TLB_M
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#define PTE_G TLB_G
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#define PTE_UX TLB_UX
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#define PTE_SX TLB_SX
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#define PTE_UW TLB_UW
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#define PTE_SW TLB_SW
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#define PTE_UR TLB_UR
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#define PTE_SR TLB_SR
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#endif
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/* Other PTE flags */
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@ -144,16 +144,16 @@
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#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
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#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */
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#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */
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#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
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#define SPR_USPRG0 0x100 /* 4.8 User SPR General 0 */
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#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
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#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
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#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
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#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
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#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
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#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
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#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
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#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
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#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
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#define SPR_SPRG4 0x114 /* 4.8 SPR General 4 */
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#define SPR_SPRG5 0x115 /* 4.8 SPR General 5 */
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#define SPR_SPRG6 0x116 /* 4.8 SPR General 6 */
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#define SPR_SPRG7 0x117 /* 4.8 SPR General 7 */
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#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */
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#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */
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#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
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@ -227,6 +227,23 @@
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#define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME)
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#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
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#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
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#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
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#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
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#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
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#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
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#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
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#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
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#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
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#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
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#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
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#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
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#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
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#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
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#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
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#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
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#define DBSR_RET 0x00008000 /* Return debug event. */
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#define SPR_EPCR 0x133
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#define EPCR_EXTGS 0x80000000
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#define EPCR_DTLBGS 0x40000000
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@ -239,10 +256,21 @@
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#define EPCR_DGTMI 0x00800000
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#define EPCR_DMIUH 0x00400000
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#define EPCR_PMGS 0x00200000
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#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
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#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
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#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
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#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
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#define SPR_IAC3 0x13a /* ..8 Instruction Address Compare 3 */
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#define SPR_IAC4 0x13b /* ..8 Instruction Address Compare 4 */
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#define SPR_HSRR0 0x13a
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#define SPR_HSRR1 0x13b
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#define SPR_LPCR 0x13e /* Logical Partitioning Control */
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#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
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#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
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#define SPR_DVC1 0x13e /* ..8 Data Value Compare 1 */
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#define SPR_DVC2 0x13f /* ..8 Data Value Compare 2 */
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#define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */
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#define LPCR_LPES 0x008 /* Bit 60 */
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#define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */
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#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */
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@ -251,7 +279,7 @@
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#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */
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#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
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/* Maintenance exceptions */
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#define SPR_LPID 0x13f /* Logical Partitioning Control */
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#define SPR_LPID 0x13f /* .6. Logical Partitioning Control */
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#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */
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#define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */
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@ -451,18 +479,11 @@
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#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
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#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
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#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
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#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
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#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */
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#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
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#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
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#define SPR_PID 0x3b1 /* 4.. Process ID */
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#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
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#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
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#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
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#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
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#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
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#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
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#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
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#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */
|
||||
#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
|
||||
#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
|
||||
@ -482,11 +503,8 @@
|
||||
#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
|
||||
#define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */
|
||||
#define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */
|
||||
#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
|
||||
#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
|
||||
#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
|
||||
#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
|
||||
#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
|
||||
#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
|
||||
#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */
|
||||
#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */
|
||||
@ -494,24 +512,17 @@
|
||||
#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */
|
||||
#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */
|
||||
|
||||
#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
|
||||
#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */
|
||||
#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */
|
||||
#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
|
||||
#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
|
||||
#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
|
||||
#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
|
||||
#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
|
||||
#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
|
||||
#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
|
||||
#if defined(BOOKE_PPC4XX)
|
||||
#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
|
||||
#else
|
||||
#define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */
|
||||
#endif
|
||||
#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
|
||||
#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
|
||||
#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
|
||||
#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
|
||||
#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
|
||||
|
||||
@ -550,9 +561,6 @@
|
||||
#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
|
||||
#define TCR_ARE 0x00400000 /* Auto Reload Enable */
|
||||
|
||||
#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
|
||||
#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
|
||||
#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
|
||||
#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
|
||||
#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
|
||||
#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */
|
||||
@ -564,54 +572,9 @@
|
||||
#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */
|
||||
|
||||
#if defined(AIM)
|
||||
#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
|
||||
#define DBSR_IC 0x80000000 /* Instruction completion debug event */
|
||||
#define DBSR_BT 0x40000000 /* Branch Taken debug event */
|
||||
#define DBSR_EDE 0x20000000 /* Exception debug event */
|
||||
#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
|
||||
#define DBSR_UDE 0x08000000 /* Unconditional debug event */
|
||||
#define DBSR_IA1 0x04000000 /* IAC1 debug event */
|
||||
#define DBSR_IA2 0x02000000 /* IAC2 debug event */
|
||||
#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
|
||||
#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
|
||||
#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
|
||||
#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
|
||||
#define DBSR_IDE 0x00100000 /* Imprecise debug event */
|
||||
#define DBSR_IA3 0x00080000 /* IAC3 debug event */
|
||||
#define DBSR_IA4 0x00040000 /* IAC4 debug event */
|
||||
#define DBSR_MRR 0x00000300 /* Most recent reset */
|
||||
#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
|
||||
#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
|
||||
#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
|
||||
#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
|
||||
#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
|
||||
#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
|
||||
#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
|
||||
#elif defined(BOOKE)
|
||||
#define SPR_PIR 0x11e /* ..8 Processor Identification Register */
|
||||
#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
|
||||
#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
|
||||
#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
|
||||
#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
|
||||
#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
|
||||
#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
|
||||
#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
|
||||
#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
|
||||
#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
|
||||
#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
|
||||
#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
|
||||
#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
|
||||
#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
|
||||
#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
|
||||
#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
|
||||
#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
|
||||
#define DBSR_RET 0x00008000 /* Return debug event. */
|
||||
#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
|
||||
#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
|
||||
#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
|
||||
#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
|
||||
#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
|
||||
#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
|
||||
#endif
|
||||
|
||||
#define DBCR0_EDM 0x80000000 /* External Debug Mode */
|
||||
@ -724,8 +687,6 @@
|
||||
#define L3CR_PMEN 0x00000004
|
||||
#define L3CR_PMSIZ 0x00000003
|
||||
|
||||
#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
|
||||
#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
|
||||
#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
|
||||
#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
|
||||
#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
|
||||
@ -783,15 +744,6 @@
|
||||
#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */
|
||||
#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */
|
||||
|
||||
#define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */
|
||||
#define MMUCR_SWOA (0x80000000 >> 7)
|
||||
#define MMUCR_U1TE (0x80000000 >> 9)
|
||||
#define MMUCR_U2SWOAE (0x80000000 >> 10)
|
||||
#define MMUCR_DULXE (0x80000000 >> 12)
|
||||
#define MMUCR_IULXE (0x80000000 >> 13)
|
||||
#define MMUCR_STS (0x80000000 >> 15)
|
||||
#define MMUCR_STID_MASK (0xFF000000 >> 24)
|
||||
|
||||
#define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */
|
||||
#define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */
|
||||
#define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */
|
||||
|
||||
@ -156,56 +156,6 @@ void tlb1_inval_entry(unsigned int);
|
||||
void tlb1_init(void);
|
||||
#endif /* !LOCORE */
|
||||
|
||||
#elif defined(BOOKE_PPC4XX)
|
||||
|
||||
/* TLB Words */
|
||||
#define TLB_PAGEID 0
|
||||
#define TLB_XLAT 1
|
||||
#define TLB_ATTRIB 2
|
||||
|
||||
/* Page identification fields */
|
||||
#define TLB_EPN_MASK (0xFFFFFC00 >> 0)
|
||||
#define TLB_VALID (0x80000000 >> 22)
|
||||
#define TLB_TS (0x80000000 >> 23)
|
||||
#define TLB_SIZE_1K (0x00000000 >> 24)
|
||||
#define TLB_SIZE_MASK (0xF0000000 >> 24)
|
||||
|
||||
/* Translation fields */
|
||||
#define TLB_RPN_MASK (0xFFFFFC00 >> 0)
|
||||
#define TLB_ERPN_MASK (0xF0000000 >> 28)
|
||||
|
||||
/* Storage attribute and access control fields */
|
||||
#define TLB_WL1 (0x80000000 >> 11)
|
||||
#define TLB_IL1I (0x80000000 >> 12)
|
||||
#define TLB_IL1D (0x80000000 >> 13)
|
||||
#define TLB_IL2I (0x80000000 >> 14)
|
||||
#define TLB_IL2D (0x80000000 >> 15)
|
||||
#define TLB_U0 (0x80000000 >> 16)
|
||||
#define TLB_U1 (0x80000000 >> 17)
|
||||
#define TLB_U2 (0x80000000 >> 18)
|
||||
#define TLB_U3 (0x80000000 >> 19)
|
||||
#define TLB_W (0x80000000 >> 20)
|
||||
#define TLB_I (0x80000000 >> 21)
|
||||
#define TLB_M (0x80000000 >> 22)
|
||||
#define TLB_G (0x80000000 >> 23)
|
||||
#define TLB_E (0x80000000 >> 24)
|
||||
#define TLB_UX (0x80000000 >> 26)
|
||||
#define TLB_UW (0x80000000 >> 27)
|
||||
#define TLB_UR (0x80000000 >> 28)
|
||||
#define TLB_SX (0x80000000 >> 29)
|
||||
#define TLB_SW (0x80000000 >> 30)
|
||||
#define TLB_SR (0x80000000 >> 31)
|
||||
#define TLB_SIZE 64
|
||||
|
||||
#define TLB_SIZE_4K (0x10000000 >> 24)
|
||||
#define TLB_SIZE_16K (0x20000000 >> 24)
|
||||
#define TLB_SIZE_64K (0x30000000 >> 24)
|
||||
#define TLB_SIZE_256K (0x40000000 >> 24)
|
||||
#define TLB_SIZE_1M (0x50000000 >> 24)
|
||||
#define TLB_SIZE_16M (0x70000000 >> 24)
|
||||
#define TLB_SIZE_256M (0x90000000 >> 24)
|
||||
#define TLB_SIZE_1G (0xA0000000 >> 24)
|
||||
|
||||
#endif /* BOOKE_E500 */
|
||||
|
||||
#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
|
||||
|
||||
@ -425,11 +425,7 @@ const struct specialreg sprregs[] = {
|
||||
{ 0x019, "sdr1" },
|
||||
{ 0x01a, "srr0" },
|
||||
{ 0x01b, "srr1" },
|
||||
#ifdef BOOKE_PPC4XX
|
||||
{ 0x100, "usprg0" },
|
||||
#else
|
||||
{ 0x100, "vrsave" },
|
||||
#endif
|
||||
{ 0x110, "sprg0" },
|
||||
{ 0x111, "sprg1" },
|
||||
{ 0x112, "sprg2" },
|
||||
@ -496,14 +492,6 @@ const struct specialreg sprregs[] = {
|
||||
{ 0x3db, "pit" },
|
||||
{ 0x3de, "srr2" },
|
||||
{ 0x3df, "srr3" },
|
||||
#ifdef BOOKE_PPC4XX
|
||||
{ 0x3f0, "dbsr" },
|
||||
{ 0x3f2, "dbcr0" },
|
||||
{ 0x3f4, "iac1" },
|
||||
{ 0x3f5, "iac2" },
|
||||
{ 0x3f6, "dac1" },
|
||||
{ 0x3f7, "dac2" },
|
||||
#else
|
||||
{ 0x3f0, "hid0" },
|
||||
{ 0x3f1, "hid1" },
|
||||
{ 0x3f2, "iabr" },
|
||||
@ -511,7 +499,6 @@ const struct specialreg sprregs[] = {
|
||||
{ 0x3f5, "dabr" },
|
||||
{ 0x3f6, "msscr0" },
|
||||
{ 0x3f7, "msscr1" },
|
||||
#endif
|
||||
{ 0x3f9, "l2cr" },
|
||||
{ 0x3fa, "dccr" },
|
||||
{ 0x3fb, "iccr" },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user