Even though BIOS writer's guide recommends cpuid instruction of Cyrix
6x86MX CPU is enabled (BIOS should not disable it), some BIOS disables it via CCR4. In this case, cpu variable becomes CPU_486 and identblue() is called. Because Cyrix 6x86MX has MSR and doesn't have MSR1002, wrmsr instruction generates general protection fault. Tested by: Simon Coggins <chaos@ultra.net.au>
This commit is contained in:
KATO Takenori
parent
44626f8fec
commit
88a92ff10e
@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.37 1998/01/03 05:36:40 obrien Exp $
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* $Id: identcpu.c,v 1.38 1998/01/03 05:43:37 obrien Exp $
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*/
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#include "opt_cpu.h"
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@ -55,10 +55,14 @@
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#include <i386/isa/intr_machdep.h>
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#define IDENTBLUE_CYRIX486 0
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#define IDENTBLUE_IBMCPU 1
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#define IDENTBLUE_CYRIXM2 2
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/* XXX - should be in header file */
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void i486_bzero __P((void *buf, size_t len));
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void printcpuinfo(void); /* XXX should be in different header file */
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void printcpuinfo(void); /* XXX should be in different header file */
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void finishidentcpu(void);
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void earlysetcpuclass(void);
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void panicifcpuunsupported(void);
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@ -534,21 +538,38 @@ panicifcpuunsupported(void)
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static volatile u_int trap_by_wrmsr;
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/*
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* Special exception 16 handler.
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* Special exception 6 handler.
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* The wrmsr instruction generates invalid opcodes fault on 486-class
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* Cyrix CPU. Stacked eip register points the wrmsr instruction in the
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* function identblue() when this handler is called. Stacked eip should
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* be advanced.
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*/
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inthand_t bluetrap;
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inthand_t bluetrap6;
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asm
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("
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.text
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.p2align 2,0x90
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" __XSTRING(CNAME(bluetrap)) ":
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" __XSTRING(CNAME(bluetrap6)) ":
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ss
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movl $0xa8c1d," __XSTRING(CNAME(trap_by_wrmsr)) " # Don't ask meaning of the number :-).
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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movl $0xa8c1d," __XSTRING(CNAME(trap_by_wrmsr)) "
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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iret
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");
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/*
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* Special exception 13 handler.
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* Accessing non-existent MSR generates general protection fault.
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*/
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inthand_t bluetrap13;
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asm
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("
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.text
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.p2align 2,0x90
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" __XSTRING(CNAME(bluetrap13)) ":
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ss
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movl $0xa89c4," __XSTRING(CNAME(trap_by_wrmsr)) "
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popl %eax # discard errorcode.
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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iret
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");
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@ -565,19 +586,29 @@ identblue(void)
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{
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trap_by_wrmsr = 0;
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/*
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* Cyrix 486-class CPU does not support wrmsr instruction.
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* The wrmsr instruction causes invalid opcode fault, and exception
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* will be trapped by bluetrap() on Cyrix 486-class CPU. The bluetrap()
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* set the magic number to trap_by_wrmsr.
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* The wrmsr instruction generates invalid opcode fault, and exception
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* will be trapped by bluetrap6() on Cyrix 486-class CPU. The
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* bluetrap6() set the magic number to trap_by_wrmsr.
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*/
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setidt(6, bluetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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wrmsr(0x1002, 0x03000000LL); /* Fault on Cyrix 486-class CPU. */
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setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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/*
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* Certain BIOS disables cpuid instructnion of Cyrix 6x86MX CPU.
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* In this case, wrmsr generates general protection fault, and
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* exception will be trapped by bluetrap13().
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*/
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setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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wrmsr(0x1002, 0x03000000LL); /* Cyrix CPU generates fault. */
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if (trap_by_wrmsr == 0xa8c1d)
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return 0; /* Cyrix CPU sets the magic number. */
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return 1; /* IBM Blue Lightnig CPU */
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return IDENTBLUE_CYRIX486;
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else if (trap_by_wrmsr == 0xa89c4)
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return IDENTBLUE_CYRIXM2;
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return IDENTBLUE_IBMCPU;
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}
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@ -632,6 +663,7 @@ identifycyrix(void)
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void
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finishidentcpu(void)
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{
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int isblue = 0;
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if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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if (cpu == CPU_486) {
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@ -640,7 +672,8 @@ finishidentcpu(void)
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* - CPU does not support cpuid instruction.
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* - Cyrix/IBM CPU is detected.
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*/
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if (identblue()) {
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isblue = identblue();
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if (isblue == IDENTBLUE_IBMCPU) {
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strcpy(cpu_vendor, "IBM");
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cpu = CPU_BLUE;
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return;
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@ -686,6 +719,11 @@ finishidentcpu(void)
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default:
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/* M2 and later CPUs are treated as M2. */
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cpu = CPU_M2;
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/*
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* XXX
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* Execute cpuid instrunction here and fix cpu_id and
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* cpu_feature variables.
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*/
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break;
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}
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}
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@ -35,7 +35,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
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* $Id: machdep.c,v 1.282 1998/01/22 17:29:26 dyson Exp $
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* $Id: machdep.c,v 1.283 1998/01/24 02:00:47 dyson Exp $
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*/
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#include "apm.h"
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@ -1225,6 +1225,7 @@ init386(first)
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finishidentcpu(); /* Final stage of CPU initialization */
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setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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initializecpu(); /* Initialize CPU registers */
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/* Use BIOS values stored in RTC CMOS RAM, since probing
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@ -36,7 +36,7 @@
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $Id: identcpu.c,v 1.37 1998/01/03 05:36:40 obrien Exp $
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* $Id: identcpu.c,v 1.38 1998/01/03 05:43:37 obrien Exp $
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*/
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#include "opt_cpu.h"
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@ -55,10 +55,14 @@
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#include <i386/isa/intr_machdep.h>
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#define IDENTBLUE_CYRIX486 0
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#define IDENTBLUE_IBMCPU 1
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#define IDENTBLUE_CYRIXM2 2
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/* XXX - should be in header file */
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void i486_bzero __P((void *buf, size_t len));
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void printcpuinfo(void); /* XXX should be in different header file */
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void printcpuinfo(void); /* XXX should be in different header file */
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void finishidentcpu(void);
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void earlysetcpuclass(void);
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void panicifcpuunsupported(void);
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@ -534,21 +538,38 @@ panicifcpuunsupported(void)
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static volatile u_int trap_by_wrmsr;
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/*
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* Special exception 16 handler.
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* Special exception 6 handler.
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* The wrmsr instruction generates invalid opcodes fault on 486-class
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* Cyrix CPU. Stacked eip register points the wrmsr instruction in the
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* function identblue() when this handler is called. Stacked eip should
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* be advanced.
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*/
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inthand_t bluetrap;
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inthand_t bluetrap6;
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asm
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("
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.text
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.p2align 2,0x90
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" __XSTRING(CNAME(bluetrap)) ":
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" __XSTRING(CNAME(bluetrap6)) ":
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ss
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movl $0xa8c1d," __XSTRING(CNAME(trap_by_wrmsr)) " # Don't ask meaning of the number :-).
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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movl $0xa8c1d," __XSTRING(CNAME(trap_by_wrmsr)) "
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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iret
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");
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/*
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* Special exception 13 handler.
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* Accessing non-existent MSR generates general protection fault.
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*/
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inthand_t bluetrap13;
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asm
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("
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.text
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.p2align 2,0x90
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" __XSTRING(CNAME(bluetrap13)) ":
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ss
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movl $0xa89c4," __XSTRING(CNAME(trap_by_wrmsr)) "
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popl %eax # discard errorcode.
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addl $2, (%esp) # I know wrmsr is a 2-bytes instruction.
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iret
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");
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@ -565,19 +586,29 @@ identblue(void)
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{
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trap_by_wrmsr = 0;
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/*
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* Cyrix 486-class CPU does not support wrmsr instruction.
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* The wrmsr instruction causes invalid opcode fault, and exception
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* will be trapped by bluetrap() on Cyrix 486-class CPU. The bluetrap()
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* set the magic number to trap_by_wrmsr.
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* The wrmsr instruction generates invalid opcode fault, and exception
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* will be trapped by bluetrap6() on Cyrix 486-class CPU. The
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* bluetrap6() set the magic number to trap_by_wrmsr.
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*/
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setidt(6, bluetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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wrmsr(0x1002, 0x03000000LL); /* Fault on Cyrix 486-class CPU. */
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setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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/*
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* Certain BIOS disables cpuid instructnion of Cyrix 6x86MX CPU.
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* In this case, wrmsr generates general protection fault, and
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* exception will be trapped by bluetrap13().
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*/
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setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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wrmsr(0x1002, 0x03000000LL); /* Cyrix CPU generates fault. */
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if (trap_by_wrmsr == 0xa8c1d)
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return 0; /* Cyrix CPU sets the magic number. */
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return 1; /* IBM Blue Lightnig CPU */
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return IDENTBLUE_CYRIX486;
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else if (trap_by_wrmsr == 0xa89c4)
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return IDENTBLUE_CYRIXM2;
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return IDENTBLUE_IBMCPU;
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}
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@ -632,6 +663,7 @@ identifycyrix(void)
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void
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finishidentcpu(void)
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{
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int isblue = 0;
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if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
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if (cpu == CPU_486) {
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@ -640,7 +672,8 @@ finishidentcpu(void)
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* - CPU does not support cpuid instruction.
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* - Cyrix/IBM CPU is detected.
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*/
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if (identblue()) {
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isblue = identblue();
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if (isblue == IDENTBLUE_IBMCPU) {
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strcpy(cpu_vendor, "IBM");
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cpu = CPU_BLUE;
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return;
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@ -686,6 +719,11 @@ finishidentcpu(void)
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default:
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/* M2 and later CPUs are treated as M2. */
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cpu = CPU_M2;
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/*
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* XXX
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* Execute cpuid instrunction here and fix cpu_id and
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* cpu_feature variables.
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*/
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break;
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}
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}
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@ -35,7 +35,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
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* $Id: machdep.c,v 1.282 1998/01/22 17:29:26 dyson Exp $
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* $Id: machdep.c,v 1.283 1998/01/24 02:00:47 dyson Exp $
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*/
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#include "apm.h"
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@ -1225,6 +1225,7 @@ init386(first)
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finishidentcpu(); /* Final stage of CPU initialization */
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setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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initializecpu(); /* Initialize CPU registers */
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/* Use BIOS values stored in RTC CMOS RAM, since probing
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@ -35,7 +35,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
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* $Id: machdep.c,v 1.70 1998/01/24 03:15:37 kato Exp $
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* $Id: machdep.c,v 1.71 1998/01/24 06:53:32 kato Exp $
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*/
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#include "apm.h"
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@ -1249,6 +1249,7 @@ init386(first)
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finishidentcpu(); /* Final stage of CPU initialization */
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setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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initializecpu(); /* Initialize CPU registers */
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#ifdef PC98
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@ -35,7 +35,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
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* $Id: machdep.c,v 1.70 1998/01/24 03:15:37 kato Exp $
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* $Id: machdep.c,v 1.71 1998/01/24 06:53:32 kato Exp $
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*/
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#include "apm.h"
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@ -1249,6 +1249,7 @@ init386(first)
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finishidentcpu(); /* Final stage of CPU initialization */
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setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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initializecpu(); /* Initialize CPU registers */
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#ifdef PC98
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