fu740_pci_dw: Add SiFive FU740 PCIe controller driver
Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D31033
This commit is contained in:
Jessica Clarke
parent
b47e5c5dbe
commit
896e217a0e
@ -5,6 +5,8 @@ cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${
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crypto/des/des_enc.c optional netsmb
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dev/ofw/ofw_cpu.c optional fdt
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dev/ofw/ofw_pcib.c optional pci fdt
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dev/pci/pci_dw.c optional pci fdt
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dev/pci/pci_dw_if.m optional pci fdt
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dev/pci/pci_host_generic.c optional pci
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dev/pci/pci_host_generic_fdt.c optional pci fdt
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dev/uart/uart_cpu_fdt.c optional uart fdt
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@ -177,6 +177,7 @@ options FDT
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makeoptions MODULES_EXTRA+="dtb/sifive"
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# SiFive device drivers
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device fu740_pci_dw
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device sifive_gpio
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device sifive_spi
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include "../sifive/std.sifive"
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@ -1,6 +1,7 @@
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# $FreeBSD$
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riscv/sifive/fe310_aon.c optional fe310aon
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riscv/sifive/fu740_pci_dw.c optional fu740_pci_dw pci fdt
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riscv/sifive/sifive_gpio.c optional sifive_gpio gpio
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riscv/sifive/sifive_prci.c standard
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riscv/sifive/sifive_spi.c optional sifive_spi spibus
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465
sys/riscv/sifive/fu740_pci_dw.c
Normal file
465
sys/riscv/sifive/fu740_pci_dw.c
Normal file
@ -0,0 +1,465 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright 2021 Jessica Clarke <jrtc27@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* SiFive FU740 DesignWare PCIe driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/gpio.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofwpci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_dw.h>
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#include "pcib_if.h"
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#include "pci_dw_if.h"
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#define FUDW_PHYS 2
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#define FUDW_LANES_PER_PHY 4
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#define FUDW_MGMT_PERST_N 0x0
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#define FUDW_MGMT_LTSSM_EN 0x10
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#define FUDW_MGMT_HOLD_PHY_RST 0x18
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#define FUDW_MGMT_DEVICE_TYPE 0x708
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#define FUDW_MGMT_DEVICE_TYPE_RC 0x4
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#define FUDW_MGMT_PHY_CR_PARA_REG(_n, _r) \
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(0x860 + (_n) * 0x40 + FUDW_MGMT_PHY_CR_PARA_##_r)
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#define FUDW_MGMT_PHY_CR_PARA_ADDR 0x0
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#define FUDW_MGMT_PHY_CR_PARA_READ_EN 0x10
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#define FUDW_MGMT_PHY_CR_PARA_READ_DATA 0x18
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#define FUDW_MGMT_PHY_CR_PARA_SEL 0x20
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#define FUDW_MGMT_PHY_CR_PARA_WRITE_DATA 0x28
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#define FUDW_MGMT_PHY_CR_PARA_WRITE_EN 0x30
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#define FUDW_MGMT_PHY_CR_PARA_ACK 0x38
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#define FUDW_MGMT_PHY_LANE(_n) (0x1008 + (_n) * 0x100)
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#define FUDW_MGMT_PHY_LANE_CDR_TRACK_EN (1 << 0)
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#define FUDW_MGMT_PHY_LANE_LOS_THRESH (1 << 5)
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#define FUDW_MGMT_PHY_LANE_TERM_EN (1 << 9)
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#define FUDW_MGMT_PHY_LANE_TERM_ACDC (1 << 10)
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#define FUDW_MGMT_PHY_LANE_EN (1 << 11)
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#define FUDW_MGMT_PHY_LANE_INIT \
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(FUDW_MGMT_PHY_LANE_CDR_TRACK_EN | FUDW_MGMT_PHY_LANE_LOS_THRESH | \
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FUDW_MGMT_PHY_LANE_TERM_EN | FUDW_MGMT_PHY_LANE_TERM_ACDC | \
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FUDW_MGMT_PHY_LANE_EN)
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#define FUDW_DBI_PORT_DBG1 0x72c
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#define FUDW_DBI_PORT_DBG1_LINK_UP (1 << 4)
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#define FUDW_DBI_PORT_DBG1_LINK_IN_TRAINING (1 << 29)
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struct fupci_softc {
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struct pci_dw_softc dw_sc;
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device_t dev;
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struct resource *mgmt_res;
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gpio_pin_t porst_pin;
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gpio_pin_t pwren_pin;
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clk_t pcie_aux_clk;
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hwreset_t pcie_aux_rst;
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};
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#define FUDW_MGMT_READ(_sc, _o) bus_read_4((_sc)->mgmt_res, (_o))
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#define FUDW_MGMT_WRITE(_sc, _o, _v) bus_write_4((_sc)->mgmt_res, (_o), (_v))
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static struct ofw_compat_data compat_data[] = {
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{ "sifive,fu740-pcie", 1 },
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{ NULL, 0 },
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};
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/* Currently unused; included for completeness */
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static int __unused
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fupci_phy_read(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t *val)
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{
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unsigned timeout;
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uint32_t ack;
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 1);
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timeout = 10;
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do {
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ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
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if (ack != 0)
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break;
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DELAY(10);
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} while (--timeout > 0);
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if (timeout == 0) {
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device_printf(sc->dev, "Timeout waiting for read ACK\n");
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return (ETIMEDOUT);
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}
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*val = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_DATA));
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 0);
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timeout = 10;
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do {
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ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
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if (ack == 0)
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break;
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DELAY(10);
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} while (--timeout > 0);
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if (timeout == 0) {
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device_printf(sc->dev, "Timeout waiting for read un-ACK\n");
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return (ETIMEDOUT);
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}
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return (0);
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}
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static int
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fupci_phy_write(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t val)
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{
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unsigned timeout;
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uint32_t ack;
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_DATA), val);
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 1);
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timeout = 10;
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do {
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ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
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if (ack != 0)
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break;
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DELAY(10);
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} while (--timeout > 0);
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if (timeout == 0) {
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device_printf(sc->dev, "Timeout waiting for write ACK\n");
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return (ETIMEDOUT);
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}
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 0);
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timeout = 10;
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do {
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ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
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if (ack == 0)
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break;
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DELAY(10);
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} while (--timeout > 0);
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if (timeout == 0) {
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device_printf(sc->dev, "Timeout waiting for write un-ACK\n");
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return (ETIMEDOUT);
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}
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return (0);
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}
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static int
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fupci_phy_init(struct fupci_softc *sc)
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{
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device_t dev;
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int error, phy, lane;
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dev = sc->dev;
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/* Assert core power-on reset (active low) */
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error = gpio_pin_set_active(sc->porst_pin, false);
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if (error != 0) {
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device_printf(dev, "Cannot assert power-on reset: %d\n",
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error);
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return (error);
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}
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/* Assert PERST_N */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 0);
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/* Enable power */
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error = gpio_pin_set_active(sc->pwren_pin, true);
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if (error != 0) {
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device_printf(dev, "Cannot enable power: %d\n", error);
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return (error);
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}
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/* Hold PERST for 100ms as per the PCIe spec */
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DELAY(100);
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/* Deassert PERST_N */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 1);
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/* Deassert core power-on reset (active low) */
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error = gpio_pin_set_active(sc->porst_pin, true);
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if (error != 0) {
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device_printf(dev, "Cannot deassert power-on reset: %d\n",
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error);
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return (error);
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}
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/* Enable the aux clock */
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error = clk_enable(sc->pcie_aux_clk);
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if (error != 0) {
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device_printf(dev, "Cannot enable aux clock: %d\n", error);
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return (error);
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}
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/* Hold LTSSM in reset whilst initialising the PHYs */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_HOLD_PHY_RST, 1);
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/* Deassert the aux reset */
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error = hwreset_deassert(sc->pcie_aux_rst);
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if (error != 0) {
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device_printf(dev, "Cannot deassert aux reset: %d\n", error);
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return (error);
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}
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/* Enable control register interface */
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for (phy = 0; phy < FUDW_PHYS; ++phy)
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, SEL), 1);
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/* Wait for enable to take effect */
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DELAY(1);
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/* Initialise lane configuration */
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for (phy = 0; phy < FUDW_PHYS; ++phy) {
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for (lane = 0; lane < FUDW_LANES_PER_PHY; ++lane)
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fupci_phy_write(sc, phy, FUDW_MGMT_PHY_LANE(lane),
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FUDW_MGMT_PHY_LANE_INIT);
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}
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/* Disable the aux clock whilst taking the LTSSM out of reset */
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error = clk_disable(sc->pcie_aux_clk);
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if (error != 0) {
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device_printf(dev, "Cannot disable aux clock: %d\n", error);
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return (error);
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}
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/* Take LTSSM out of reset */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_HOLD_PHY_RST, 0);
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/* Enable the aux clock again */
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error = clk_enable(sc->pcie_aux_clk);
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if (error != 0) {
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device_printf(dev, "Cannot re-enable aux clock: %d\n", error);
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return (error);
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}
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/* Put the controller in Root Complex mode */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_DEVICE_TYPE, FUDW_MGMT_DEVICE_TYPE_RC);
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return (0);
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}
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static void
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fupci_dbi_protect(struct fupci_softc *sc, bool protect)
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{
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uint32_t reg;
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reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1);
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if (protect)
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reg &= ~DBI_RO_WR_EN;
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else
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reg |= DBI_RO_WR_EN;
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pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);
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}
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static int
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fupci_init(struct fupci_softc *sc)
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{
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/* Enable 32-bit I/O window */
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fupci_dbi_protect(sc, false);
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pci_dw_dbi_wr2(sc->dev, PCIR_IOBASEL_1,
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(PCIM_BRIO_32 << 8) | PCIM_BRIO_32);
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fupci_dbi_protect(sc, true);
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/* Enable LTSSM */
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FUDW_MGMT_WRITE(sc, FUDW_MGMT_LTSSM_EN, 1);
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return (0);
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}
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static int
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fupci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "SiFive FU740 PCIe Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fupci_attach(device_t dev)
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{
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struct fupci_softc *sc;
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phandle_t node;
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int error, rid;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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rid = 0;
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error = ofw_bus_find_string_index(node, "reg-names", "dbi", &rid);
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if (error != 0) {
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device_printf(dev, "Cannot get DBI memory: %d\n", error);
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goto fail;
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}
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sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->dw_sc.dbi_res == NULL) {
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device_printf(dev, "Cannot allocate DBI memory\n");
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error = ENXIO;
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goto fail;
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}
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rid = 0;
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error = ofw_bus_find_string_index(node, "reg-names", "mgmt", &rid);
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if (error != 0) {
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device_printf(dev, "Cannot get management space memory: %d\n",
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error);
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goto fail;
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}
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sc->mgmt_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mgmt_res == NULL) {
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device_printf(dev, "Cannot allocate management space memory\n");
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error = ENXIO;
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goto fail;
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}
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error = gpio_pin_get_by_ofw_property(dev, node, "reset-gpios",
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&sc->porst_pin);
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/* Old U-Boot device tree uses perstn-gpios */
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if (error == ENOENT)
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error = gpio_pin_get_by_ofw_property(dev, node, "perstn-gpios",
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&sc->porst_pin);
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if (error != 0) {
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device_printf(dev, "Cannot get power-on reset GPIO: %d\n",
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error);
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goto fail;
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}
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error = gpio_pin_setflags(sc->porst_pin, GPIO_PIN_OUTPUT);
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if (error != 0) {
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device_printf(dev, "Cannot configure power-on reset GPIO: %d\n",
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error);
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goto fail;
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}
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error = gpio_pin_get_by_ofw_property(dev, node, "pwren-gpios",
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&sc->pwren_pin);
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if (error != 0) {
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device_printf(dev, "Cannot get power enable GPIO: %d\n",
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error);
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goto fail;
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}
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error = gpio_pin_setflags(sc->pwren_pin, GPIO_PIN_OUTPUT);
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if (error != 0) {
|
||||
device_printf(dev, "Cannot configure power enable GPIO: %d\n",
|
||||
error);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
error = clk_get_by_ofw_name(dev, node, "pcie_aux", &sc->pcie_aux_clk);
|
||||
/* Old U-Boot device tree uses pcieaux */
|
||||
if (error == ENOENT)
|
||||
error = clk_get_by_ofw_name(dev, node, "pcieaux",
|
||||
&sc->pcie_aux_clk);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "Cannot get aux clock: %d\n", error);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
error = hwreset_get_by_ofw_idx(dev, node, 0, &sc->pcie_aux_rst);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "Cannot get aux reset: %d\n", error);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
error = fupci_phy_init(sc);
|
||||
if (error != 0)
|
||||
goto fail;
|
||||
|
||||
error = pci_dw_init(dev);
|
||||
if (error != 0)
|
||||
goto fail;
|
||||
|
||||
error = fupci_init(sc);
|
||||
if (error != 0)
|
||||
goto fail;
|
||||
|
||||
return (bus_generic_attach(dev));
|
||||
|
||||
fail:
|
||||
/* XXX Cleanup */
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
fupci_get_link(device_t dev, bool *status)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = pci_dw_dbi_rd4(dev, FUDW_DBI_PORT_DBG1);
|
||||
*status = (reg & FUDW_DBI_PORT_DBG1_LINK_UP) != 0 &&
|
||||
(reg & FUDW_DBI_PORT_DBG1_LINK_IN_TRAINING) == 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t fupci_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, fupci_probe),
|
||||
DEVMETHOD(device_attach, fupci_attach),
|
||||
|
||||
/* PCI DW interface */
|
||||
DEVMETHOD(pci_dw_get_link, fupci_get_link),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
DEFINE_CLASS_1(pcib, fupci_driver, fupci_methods,
|
||||
sizeof(struct fupci_softc), pci_dw_driver);
|
||||
static devclass_t fupci_devclass;
|
||||
DRIVER_MODULE(fu740_pci_dw, simplebus, fupci_driver, fupci_devclass,
|
||||
NULL, NULL);
|
||||
Loading…
Reference in New Issue
Block a user