Add basic support for the Radisys-specific PCI console mechanism found on the
Radisys ATCA-7220.
This commit is contained in:
Juli Mallett
parent
ed1f69514a
commit
8aff4e5fdd
@ -39,8 +39,22 @@ __FBSDID("$FreeBSD$");
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#include <contrib/octeon-sdk/cvmx.h>
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#include <contrib/octeon-sdk/cvmx-bootmem.h>
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#include <contrib/octeon-sdk/cvmx-interrupt.h>
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#include <contrib/octeon-sdk/octeon-pci-console.h>
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#ifdef OCTEON_VENDOR_RADISYS
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#define OPCIC_FLAG_RSYS (0x00000001)
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#define OPCIC_RSYS_FIFO_SIZE (0x2000)
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#endif
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struct opcic_softc {
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unsigned sc_flags;
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uint64_t sc_base_addr;
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};
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static struct opcic_softc opcic_instance;
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static cn_probe_t opcic_cnprobe;
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static cn_init_t opcic_cninit;
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static cn_term_t opcic_cnterm;
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@ -49,20 +63,46 @@ static cn_putc_t opcic_cnputc;
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static cn_grab_t opcic_cngrab;
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static cn_ungrab_t opcic_cnungrab;
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#ifdef OCTEON_VENDOR_RADISYS
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static int opcic_rsys_cngetc(struct opcic_softc *);
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static void opcic_rsys_cnputc(struct opcic_softc *, int);
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#endif
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CONSOLE_DRIVER(opcic);
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static void
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opcic_cnprobe(struct consdev *cp)
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{
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const struct cvmx_bootmem_named_block_desc *pci_console_block;
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struct opcic_softc *sc;
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sc = &opcic_instance;
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sc->sc_flags = 0;
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sc->sc_base_addr = 0;
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cp->cn_pri = CN_DEAD;
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pci_console_block = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
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if (pci_console_block == NULL)
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return;
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switch (cvmx_sysinfo_get()->board_type) {
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#ifdef OCTEON_VENDOR_RADISYS
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case CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE:
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pci_console_block =
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cvmx_bootmem_find_named_block("rsys_gbl_memory");
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if (pci_console_block != NULL) {
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sc->sc_flags |= OPCIC_FLAG_RSYS;
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sc->sc_base_addr = pci_console_block->base_addr;
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break;
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}
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#endif
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default:
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pci_console_block =
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cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
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if (pci_console_block == NULL)
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return;
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sc->sc_base_addr = pci_console_block->base_addr;
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break;
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}
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cp->cn_arg = (void *)(uintptr_t)pci_console_block->base_addr;
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cp->cn_arg = sc;
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snprintf(cp->cn_name, sizeof cp->cn_name, "opcic@%p", cp->cn_arg);
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cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL;
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}
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@ -82,13 +122,19 @@ opcic_cnterm(struct consdev *cp)
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static int
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opcic_cngetc(struct consdev *cp)
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{
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uint64_t console_desc_addr;
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struct opcic_softc *sc;
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char ch;
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int rv;
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console_desc_addr = (uintptr_t)cp->cn_arg;
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sc = cp->cn_arg;
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rv = octeon_pci_console_read(console_desc_addr, 0, &ch, 1, OCT_PCI_CON_FLAG_NONBLOCK);
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#ifdef OCTEON_VENDOR_RADISYS
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if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0)
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return (opcic_rsys_cngetc(sc));
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#endif
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rv = octeon_pci_console_read(sc->sc_base_addr, 0, &ch, 1,
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OCT_PCI_CON_FLAG_NONBLOCK);
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if (rv != 1)
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return (-1);
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return (ch);
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@ -97,14 +143,21 @@ opcic_cngetc(struct consdev *cp)
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static void
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opcic_cnputc(struct consdev *cp, int c)
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{
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uint64_t console_desc_addr;
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struct opcic_softc *sc;
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char ch;
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int rv;
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console_desc_addr = (uintptr_t)cp->cn_arg;
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sc = cp->cn_arg;
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ch = c;
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rv = octeon_pci_console_write(console_desc_addr, 0, &ch, 1, 0);
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#ifdef OCTEON_VENDOR_RADISYS
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if ((sc->sc_flags & OPCIC_FLAG_RSYS) != 0) {
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opcic_rsys_cnputc(sc, c);
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return;
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}
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#endif
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rv = octeon_pci_console_write(sc->sc_base_addr, 0, &ch, 1, 0);
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if (rv == -1)
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panic("%s: octeon_pci_console_write failed.", __func__);
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}
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@ -120,3 +173,64 @@ opcic_cnungrab(struct consdev *cp)
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{
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(void)cp;
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}
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#ifdef OCTEON_VENDOR_RADISYS
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static int
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opcic_rsys_cngetc(struct opcic_softc *sc)
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{
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uint64_t gbl_base;
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uint64_t console_base;
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uint64_t console_rbuf;
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uint64_t console_rcnt[2];
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uint16_t rcnt[2];
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uint16_t roff;
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int c;
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gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
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console_base = gbl_base + 0x10;
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console_rbuf = console_base + 0x2018;
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console_rcnt[0] = console_base + 0x08;
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console_rcnt[1] = console_base + 0x0a;
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/* Check if there is anything new in the FIFO. */
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rcnt[0] = cvmx_read64_uint16(console_rcnt[0]);
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rcnt[1] = cvmx_read64_uint16(console_rcnt[1]);
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if (rcnt[0] == rcnt[1])
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return (-1);
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/* Get first new character in the FIFO. */
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if (rcnt[0] != 0)
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roff = rcnt[0] - 1;
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else
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roff = OPCIC_RSYS_FIFO_SIZE - 1;
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c = cvmx_read64_uint8(console_rbuf + roff);
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/* Advance FIFO. */
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rcnt[1] = (rcnt[1] + 1) % OPCIC_RSYS_FIFO_SIZE;
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cvmx_write64_uint16(console_rcnt[1], rcnt[1]);
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return (c);
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}
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static void
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opcic_rsys_cnputc(struct opcic_softc *sc, int c)
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{
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uint64_t gbl_base;
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uint64_t console_base;
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uint64_t console_wbuf;
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uint64_t console_wcnt;
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uint16_t wcnt;
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gbl_base = CVMX_ADD_IO_SEG(sc->sc_base_addr);
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console_base = gbl_base + 0x10;
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console_wbuf = console_base + 0x0018;
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console_wcnt = console_base + 0x0c;
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/* Append character to FIFO. */
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wcnt = cvmx_read64_uint16(console_wcnt) % OPCIC_RSYS_FIFO_SIZE;
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cvmx_write64_uint8(console_wbuf + wcnt, (uint8_t)c);
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cvmx_write64_uint16(console_wcnt, wcnt + 1);
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}
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#endif
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